I've breadboarded this LDO design that I have sketched in my notes from a few years ago. It's an LDO circuit consisting solely of discrete components. I'm sure that I copied it from some www page, but I can't find that source now. In fact, recently I haven't found any discrete LDO design not involving an opamp. I've attached the schematic and LTSPICE model.
I'm new to this (or any) forum, so I'll be as brief as possible in this opening posting, and fill in the blanks as requested. I'm hoping to attract constructive feedback from this community that will help me move forward. I'll post more specific questions subsequently.
I intend to integrate this design around a FET load switch that's already committed to the design. These are my goals for this circuit:
- Output below 10V with input <=15V @ 2-3uA for standby operation, 10-25mA for normal operation. Precision is not crucial.
- Teeny dropout: As overvoltage represents an abnormal condition, I want the regulator to have minimal effect on the power supply when operating normally. Ie I'm looking for ZERO additional effect to the open switch that's already in the design. The FET (VP3203; Rdson=1R0) drops about 10mV in normal operation.
- Miserly power requirement: I'm aiming for 10uA max when not regulating, and not much more when supplying the (dormant) standby curcuit (requires 2-3uA; 2uF capacitance). So far I've got it down to 21uA.
- The components requiring overvoltage protection:
A 3V regulator powering the standby circuit (MCP1702-3.0); can take 13Vmax.
A couple of Al-lyte caps rated at 10V. I know, I shouldn't be cutting cap voltage tolerances that close, but let's just go with this requirement for academic reasons.
- The load circuit requires 10-20mA clean enough not to cause audible power supply hum. The Load has capacitance of around 350uF.
The attached files represent the current state, after several iterations using lower resistor values. As I increase resistor values to bring down the quiescent current, I'm finding the circuit to be increasingly sensitive to internal detail and to its environment. I get the feeling that this is par for LDO regulators.
I'm having a bit of a problem with the SPICE model: It's set up to simulate first powering the standby circuit, and subseqently the application. I've tweeked the model to behave reasonably well for this scenario. However, when I configure both standby and application circuits to power up simultaneously (by bypassing S2), the model ends up with unstable (oscillating) output. My gut tells me that this is due to an imperfection in the model... Of course my breadboard version behaves consistantly regardless of the order of powering up.
Note that I don't own a scope... I have only my DVM (and an analog one) and the backend application circuit to assess my LDO circuit. The output measures a consistent 9.7V (pretty close to the expected theoretical result), and I can hear no power supply hum (the application is a portable headphone amplifier).
I'll leave it at that for this original post. Please feel free to ask me for any clarifications, ellaborations, explanations, etc...
thanks in advance
<sigh> that was brief, wasn't it??
I'm new to this (or any) forum, so I'll be as brief as possible in this opening posting, and fill in the blanks as requested. I'm hoping to attract constructive feedback from this community that will help me move forward. I'll post more specific questions subsequently.
I intend to integrate this design around a FET load switch that's already committed to the design. These are my goals for this circuit:
- Output below 10V with input <=15V @ 2-3uA for standby operation, 10-25mA for normal operation. Precision is not crucial.
- Teeny dropout: As overvoltage represents an abnormal condition, I want the regulator to have minimal effect on the power supply when operating normally. Ie I'm looking for ZERO additional effect to the open switch that's already in the design. The FET (VP3203; Rdson=1R0) drops about 10mV in normal operation.
- Miserly power requirement: I'm aiming for 10uA max when not regulating, and not much more when supplying the (dormant) standby curcuit (requires 2-3uA; 2uF capacitance). So far I've got it down to 21uA.
- The components requiring overvoltage protection:
A 3V regulator powering the standby circuit (MCP1702-3.0); can take 13Vmax.
A couple of Al-lyte caps rated at 10V. I know, I shouldn't be cutting cap voltage tolerances that close, but let's just go with this requirement for academic reasons.
- The load circuit requires 10-20mA clean enough not to cause audible power supply hum. The Load has capacitance of around 350uF.
The attached files represent the current state, after several iterations using lower resistor values. As I increase resistor values to bring down the quiescent current, I'm finding the circuit to be increasingly sensitive to internal detail and to its environment. I get the feeling that this is par for LDO regulators.
I'm having a bit of a problem with the SPICE model: It's set up to simulate first powering the standby circuit, and subseqently the application. I've tweeked the model to behave reasonably well for this scenario. However, when I configure both standby and application circuits to power up simultaneously (by bypassing S2), the model ends up with unstable (oscillating) output. My gut tells me that this is due to an imperfection in the model... Of course my breadboard version behaves consistantly regardless of the order of powering up.
Note that I don't own a scope... I have only my DVM (and an analog one) and the backend application circuit to assess my LDO circuit. The output measures a consistent 9.7V (pretty close to the expected theoretical result), and I can hear no power supply hum (the application is a portable headphone amplifier).
I'll leave it at that for this original post. Please feel free to ask me for any clarifications, ellaborations, explanations, etc...
thanks in advance
<sigh> that was brief, wasn't it??
Attachments
-
77.3 KB Views: 182
-
4.3 KB Views: 52