# Analyze this Sequential Circuit

Thread Starter

#### lunapt

Joined Feb 2, 2013
12
http://imgur.com/k5mAjdJ

So for D1 I got = Y NOT^(Q1 v Q0) (I know its (t) for each variable, didn't include it cuz it looks really messy here)

The entity definition is Y as input, Q1, Q0 as ouput with a clock.

What would J0 and K0 be? And Do they require an entity definition of their own?

#### WBahn

Joined Mar 31, 2012
26,398
What do you mean by "entity definition"?

Are you referring to a specific HDL such as VHDL or Verilog?

If so, are we supposed to be mind readers and simply know that's what your talking about?

Your notation is a bit unusual (though far from unheard of). So is ^ a logical AND and v a logical OR? If so, then you are correct. Most people around here (there are exceptions, of course), would probably write this as

D1 = (Y')(Q0+Q1)

What's your best attempt at finding an expression for J0 and K0? That will give us a starting point to work with you from?

#### tshuck

Joined Oct 18, 2012
3,534
Unless you are generating the clock from within this circuit, it is also an input to the entity.

The terminology seems reminiscent of VHDL, it's possible the professor has referred to a subsystem as an entity to ready the student for the transition to VHDL.

I learned the ^ v notation, but dropped it shortly after... Thread Starter

#### lunapt

Joined Feb 2, 2013
12
whoops i mean clock as an input too. J0 = Q01' and k0 = Y.

#### tshuck

Joined Oct 18, 2012
3,534
I think you need to work on your notation skills, what is Q01'? Is it Q0 ANDed with 1'? Are you indicating the flip flop output in binary, Q01 and it's output is inverted?

J0 is served via a multiplexer, which is dependent on Y as the select. This means you should have two possible functions which will affect J0 when Y = 1 and Y = 0.

Thread Starter

#### lunapt

Joined Feb 2, 2013
12
I mean J0 = Q1 ' . and yes, i believe its the subsystem(?) that you mentioned. It's a box that shows the inputs and outputs. I put Y = input with Q1 and Q0 as the outputs.

Working on the state diagrams right now.

#### tshuck

Joined Oct 18, 2012
3,534
Don't forget your clock....again.... So, why is J0 = Q0' when there is a whole other option when Y = 1?

Last edited:
Thread Starter

#### lunapt

Joined Feb 2, 2013
12
Isn't that the answer I can find out making a state table? And to use the state table I think I need to use J0 = Q0'

#### tshuck

Joined Oct 18, 2012
3,534
The multiplexer passes Q0' only when Y is 0, otherwise, it passes Q0 NAND Q1.

Thread Starter

#### lunapt

Joined Feb 2, 2013
12
ohh i see it now, thank you. ( Sorry , I meant J0 = Q1 ' when Y = 0. )

the characteristic equation is JQ' + K'Q to find Q(t+1)

Replacing the variables for J0 = Q1' when Y= 0, J0 = (Q1Q0)' when Y = 1 , and K0 = Y gives:

If Y=0, Q1'Q0'+Y'Q0
If Y 1, (Q1Q0)'Q0 ' + Y'Q0

I think this is the right answer Last edited:
Thread Starter

#### lunapt

Joined Feb 2, 2013
12
I think I got it now, thanks!

Last edited:
Thread Starter

#### lunapt

Joined Feb 2, 2013
12
What is the output of this though? I can't write my FMS without knowing it.. #### WBahn

Joined Mar 31, 2012
26,398
ohh i see it now, thank you. ( Sorry , I meant J0 = Q1 ' when Y = 0. )

the characteristic equation is JQ' + K'Q to find Q(t+1)

Replacing the variables for J0 = Q1' when Y= 0, J0 = (Q1Q0)' when Y = 1 , and K0 = Y gives:

If Y=0, Q1'Q0'+Y'Q0
If Y 1, (Q1Q0)'Q0 ' + Y'Q0

I think this is the right answer You don't need to write the equations using IF this IF that.

Think about the basic characteristic equation for a 2:1 MUX

If S then D1 else D0 where D0 is the data applied to channel 0 and D1 is the data applied to channel 1. If the output is Y, then

Y = S*D1 + S'*D0

If that's not obvious to you, draw the truth table and you should have an "Ahah!" moment.

That should let you develop a single boolean expression for your output.