Here is how to raise input impedance gradually.









Now for increased gain.





This circuit cannot be used for your parameters given because the input impedance is still not high enough

but this gives yiu the basic way to resolve this kind of design.



Now here is what it is going for a gain of 10 at one time.

Notice the blue wave has severe distortion. the output is distorted.




Now using a gain of around 3 - 4 makes a nice symetrical gain on the output blue waveform. Just changing the emitter signal gain resistor from 50 ohms to 150 ohms.




Now you see why it's important to split the gain among stages. Using up to 3 stages if necassary.

Depending on the amount of gain required as well as impedances, called for.

 

Ok guys, sorry I haven't read the last couple of replies but here is what ive done so far. The labs are closing now so Ill post a schematic of what ive done and will go through the previous posts and try to learn.

The problem here is stage two. Stage one works perfectly.

 

You need to bias the stage to get the proper voltages across the load.

See if this helps any..

Here is a way that I came up with to find what bias resistors are needed to get the proper voltage across a load.

This is just my way, other people more knowledgeable can do better, but this works for me, to get ballpark values for transistor stages.

Example:

VCC = 12V.
Rload = 470 ohms
Vout pk = 3V. pk-pk = 6v.

1. Make RC =< Rload, (RC = 220 ohms)
2. VC = VCC / 2 (VC = 6v.)
3. ICQ = VC / RC (ICQ = 27mA.)

Now comes the calculations follow very carefully to get a understanding of how this works.

The collector voltage VC will be biased quiescent, at 6v.
The voltage across the Rload will then sit at 0V. due to the capacitor coupling.

Now with 3v. pk for the Vout, means that, the VC value will start out at 6v. then drop to 3v. then return to 6v. and increase to 9v. then return to 6v. and so on.
That is the output excursions.

To find out what value of RE I would need to supply the proper amount of current to acomplish this, I first consider the value of current that will need to flow through the transistor to drop the VC down to 3v.

This is done by, {(VCC - VC) / RC} = IC increase.
(12v. - 3v.) / 220 ohms = 41mA. (where 3v. is the new VC value, during that excursion.)

Now that I have the maximum amount of current needed, then I choose a voltage across the transistor (VCE) that will ensure the transistor is not saturated.)

In my example I chose 2v. for VCE.

Now RE will be calculated by taking {(VC - VCE) / IC} = RE
(3v. - 2v.) / 41mA = 24 ohms.
Where VC is the Vout excursion and IC is the increase in current during that excursion.

So now RE is established to provide the current nessary to make the VC drop to 3v. with the input signal.

Now to solve for voltage at the emitter. (VE)

When the transistor is back in quiescent state 6v. dropped across RC means quiescent current of 27mA. will flow through RE so VE will be (ICQ x RE) = 0.65v.

Now Vbe = 0.7v. for silicon transistor.

VB = VE + Vbe = (0.65v. + 0.7v.) = 1.35v.

I choose RB1 to be 10 x RE = 240 ohms.

Now ID is the current flowing through this voltage divider.

ID = (VB / RB1) = 5.6mA.

and RB2 = {(VCC - VB) / ID} = 1.9K ie.. make it 1.8K standard.

This gets it in the ballpark so after prototyping values can be adjusted as needed.

 

I analysed this circuit hours ago on another website. I cropped the schematic.
Its input impedance is much too low.
Its gain is only 3.9.
Its output swing is only 0.55V p-p.

Its output emitter follower is missing a bias resistor and an emitter resistor.

 

Update!

This is my final touch guys. Have a look at it and tell me if anything needs changing! The gain is 12.452.

I implemented on the breadboard, and everything seems to be fine. Although I didn't get much time since the labs were closing.

Once again, thanks for all the input and help from all of you. One can truly learn a lot through projects.

 

Just by looking at your waveforms on your simulator,
looks good, you have all the gain you were looking for, as well as no distortion, your input impedance is around 50K, with 100K // 100K, but probably higher due to the bootstrap effect of the Q2 base connection.

you have a nice low output impedance with respect to your load, as well as a good understanding of source split resistance, with AC decoupling to recover more amplification.

Very interestring how you returned your gate pull up voltage to the base of the BJT, some sort of feedback that appears to be working quite well. This would probably increase the input impedance better, higher, which is good, like a bootstrap feeddback.

You have come a long way in your learning about transistor stage coupling, as well as configurations.

I'm just an amature, so this is just my opinion.

Good work...

 

your input impedance is around 50K, with 100K // 100K, but probably higher due to the bootstrap effect of the Q2 base connection.

No.
The negative feedback at the input reduces the input impedance, it does not bootstrap it nor increase the input impedance.

Very interestring how you returned your gate pull up voltage to the base of the BJT, some sort of feedback that appears to be working quite well. This would probably increase the input impedance better, higher, which is good, like a bootstrap feeddback.

As above, it is negative feedback from the drain of the Mosfet to the gate which reduces the input impedance.

 

Yeh, I know, I thought about it at work this morning, and I wanted to edit my post about that, but forgot too,

its the same thing as a BJT where there is collector voltage feedback, which actually will reduce input impedance, due to the load, as being part of the input, circuit.

It's when there is a positive input signal, the signal will go to ground through the bottom 100K resistor, but also the positive signal will see the FET in pasrrallel with the bottom 100k res. and follow that to ground as well, through the FET.

That's why the positive signal see's a lower input resistance, which causes the input source resistance to become loaded due to the currents (electron) flowing from the drain of the FET, back to the input signal source.