Hello all,,,
first I'd just like to clarify that this is not me trying to let you do my project or anything like that, as a matter of fact I am actually done demonstrating my project yesterday (whew!) However for my project I mostly used a trial-and-error kinda approach but not entirely of course.
For the project we had to design a one-stage BJT or FET amplifier circuit with a dB gain of 50 and a bandwidth 100Hz - 10MHz. and then use this design to build a two-stage amplifier circuit with a gain of 100 and the same bandwidth.
My questions are:
1) How do we usually approach such a design problem (for the single-stage problem)? considering I chose the voltage divider common emitter configuration and BC182 BJT. What calculations are included to reach such a gain and cutoff frequencies?
2) Why will we most likely use a BJT not an FET transistor for such a design?
3) In our design for the two-stage amp we used an op amp buffer or an emitter follower stage between the two stages, Why do we usually do that?
4) And finally, when we used an op amp buffer between the two stages the gain was higher, why is that and is this normal? Also when we used the BJT buffer (emitter follower) between the stages the upper cut-off frequency was lower than the op-amp case, why is that?
THANKS ALL! ^^
I'd appreciate your help!
first I'd just like to clarify that this is not me trying to let you do my project or anything like that, as a matter of fact I am actually done demonstrating my project yesterday (whew!) However for my project I mostly used a trial-and-error kinda approach but not entirely of course.
For the project we had to design a one-stage BJT or FET amplifier circuit with a dB gain of 50 and a bandwidth 100Hz - 10MHz. and then use this design to build a two-stage amplifier circuit with a gain of 100 and the same bandwidth.
My questions are:
1) How do we usually approach such a design problem (for the single-stage problem)? considering I chose the voltage divider common emitter configuration and BC182 BJT. What calculations are included to reach such a gain and cutoff frequencies?
2) Why will we most likely use a BJT not an FET transistor for such a design?
3) In our design for the two-stage amp we used an op amp buffer or an emitter follower stage between the two stages, Why do we usually do that?
4) And finally, when we used an op amp buffer between the two stages the gain was higher, why is that and is this normal? Also when we used the BJT buffer (emitter follower) between the stages the upper cut-off frequency was lower than the op-amp case, why is that?
THANKS ALL! ^^
I'd appreciate your help!