# Alternative 8-bit Comparator using Verilog

Discussion in 'Programmer's Corner' started by Payat, Nov 29, 2012.

1. ### Payat Thread Starter New Member

Nov 24, 2012
1
0
Hey, so I'm new to these forums and I thought I would shoot some questions.

So, I designed an 8-bit comparator using Verilog coding and I got it to work. (Yay!) But, I found out that there was a better way to approach than the way that I designed it. So, I attempted to go this route (saving my original work, of course) and have ran into a dead end. I just cannot get past certain issues with Verilog syntax. Here is the code I have written (I figured I'd post it since it's broken anyway):
Code ( (Unknown Language)):
1.
2. module Compare8Bit (A, B, IEQ, ILT, IGT, OEQ, OLT, OGT);
3.
4. parameter nBITS = 4;
5. input [nBITS-1:0] A,B;
6. input IEQ, ILT, IGT; //inputs equal to, lesser than, and greater than, respectively
7. output OEQ, OLT, OGT; //outputs equal to, lesser than, and greater than, respectively
8.
9. wire [nBITS-1:0] EQW, LTW, GTW; //connects each exp2-bit comparator
10. genvar i;
11.
12. generate
13.   assign {A1[2*nBITS-1], A0[2*nBITS]} = A[2*nBITS-1:2*nBITS-2];
14.   assign {B1[2*nBITS-1], B0[2*nBITS]} = B[2*nBITS-1:2*nBITS-2];
15.   assign EQW[nBITS-1] = IEQ;
16.   assign LTW[nBITS-1] = ILT;
17.   assign GTW[nBITS-1] = IGT;
18.   assign OEQ = EQW[nBITS];
19.   assign OLT = LTW[nBITS];
20.   assign OGT = GTW[nBITS];
21.   for (i=nBITS; i > 0; i = i-1)
22.   begin: expandCompareAB //expandable 2-bit comparator- instantiates as many modules as needed for the bit count
23.     expandCompareAB S ({A1[2*i-1],A0[2*i-2]}, {B1[2*i-1],B0[2*i-2]}, EQW[i-1], LTW[i-1], GTW[i-1], EQW[i], LTW[i], GTW[i]);
24.   end
25. endgenerate
26. endmodule
27. [/i][/i][/i]

The idea was to make it into an expandable n-bit comparator so as to make it more versatile for any other hypothetical projects (IE: What if I needed to make a 16-bit comparator?). The immediate problems that arise are in the assign statements, I noticed but I have little understanding of the syntax used in the generate "function" and would love any help with it. expandCompare AB had no errors and generated correct timing diagrams. Thanks!

2. ### guitarguy12387 Active Member

Apr 10, 2008
359
12
Though there is probably some educational benefits to this exercise, there are much easier ways to implement this.

Something like this (first few as examples):
Code ( (Unknown Language)):
1.
2. module my_compare
3. #(parameter N = 4)
4. (
5.   input [N-1:0] A,
6.   input [N-1:0] B,
7.   output reg eq,
8.   output reg a_gt_b
9. );
10.
11.   always @ *
12.   begin
13.
14.     if (A == B)
15.       eq = 1;
16.     else
17.       eq = 0;
18.
19.     if (A > B)
20.       a_gt_b = 1;
21.     else
22.       a_gt_b = 0;
23.
24.   end
25.
26. endmodule
27.
28.
Or, even more compactly:
Code ( (Unknown Language)):
1.
2. module my_compare
3. #(parameter N = 4)
4. (
5.   input [N-1:0] A,
6.   input [N-1:0] B,
7.   output eq,
8.   output a_gt_b
9. );
10.
11.   assign eq = (A == B) ? 1 : 0;
12.   assign a_gt_b = (A > B) ? 1 : 0;
13.
14. endmodule
15.
16.
Note that this is from the top of my head... could be errors