Hey, so I'm new to these forums and I thought I would shoot some questions.
So, I designed an 8-bit comparator using Verilog coding and I got it to work. (Yay!) But, I found out that there was a better way to approach than the way that I designed it. So, I attempted to go this route (saving my original work, of course) and have ran into a dead end. I just cannot get past certain issues with Verilog syntax. Here is the code I have written (I figured I'd post it since it's broken anyway):
The idea was to make it into an expandable n-bit comparator so as to make it more versatile for any other hypothetical projects (IE: What if I needed to make a 16-bit comparator?). The immediate problems that arise are in the assign statements, I noticed but I have little understanding of the syntax used in the generate "function" and would love any help with it. expandCompare AB had no errors and generated correct timing diagrams. Thanks!
So, I designed an 8-bit comparator using Verilog coding and I got it to work. (Yay!) But, I found out that there was a better way to approach than the way that I designed it. So, I attempted to go this route (saving my original work, of course) and have ran into a dead end. I just cannot get past certain issues with Verilog syntax. Here is the code I have written (I figured I'd post it since it's broken anyway):
Rich (BB code):
module Compare8Bit (A, B, IEQ, ILT, IGT, OEQ, OLT, OGT);
parameter nBITS = 4;
input [nBITS-1:0] A,B;
input IEQ, ILT, IGT; //inputs equal to, lesser than, and greater than, respectively
output OEQ, OLT, OGT; //outputs equal to, lesser than, and greater than, respectively
wire [nBITS-1:0] EQW, LTW, GTW; //connects each exp2-bit comparator
genvar i;
generate
assign {A1[2*nBITS-1], A0[2*nBITS]} = A[2*nBITS-1:2*nBITS-2];
assign {B1[2*nBITS-1], B0[2*nBITS]} = B[2*nBITS-1:2*nBITS-2];
assign EQW[nBITS-1] = IEQ;
assign LTW[nBITS-1] = ILT;
assign GTW[nBITS-1] = IGT;
assign OEQ = EQW[nBITS];
assign OLT = LTW[nBITS];
assign OGT = GTW[nBITS];
for (i=nBITS; i > 0; i = i-1)
begin: expandCompareAB //expandable 2-bit comparator- instantiates as many modules as needed for the bit count
expandCompareAB S ({A1[2*i-1],A0[2*i-2]}, {B1[2*i-1],B0[2*i-2]}, EQW[i-1], LTW[i-1], GTW[i-1], EQW, LTW, GTW);
end
endgenerate
endmodule
The idea was to make it into an expandable n-bit comparator so as to make it more versatile for any other hypothetical projects (IE: What if I needed to make a 16-bit comparator?). The immediate problems that arise are in the assign statements, I noticed but I have little understanding of the syntax used in the generate "function" and would love any help with it. expandCompare AB had no errors and generated correct timing diagrams. Thanks!