Hi,
I'm working on simulating my project within Altera Quartus 11. I'm using VHDL code to simulate the design.
I'm giving a signal assignment to one of the inputs, but my test output on the same channel gives a different value to the one that has been assigned. The circuit and waveform are shown below:
http://img26.imageshack.us/img26/8428/circuits.png
http://imageshack.us/photo/my-images/818/waveform.png/
The two signals i'm referring to are mux_vcc (input) and mux_test (output), which are both connected to the same channel, and can be seen in the schematic. Although in my VHDL code i'm assigning mux_vcc (input) as 0, mux_test (output) is 1 at the very start of the simulation.
I was wondering if someone would please be able to help me out, as one of the purposes of my circuit is to detect the first 1 bit, and this issue means i'm unable to confirm it's performance.
Below is my signal assignments used in VHDL:
Any help would be greatly appreciated.
Thanks.
I'm working on simulating my project within Altera Quartus 11. I'm using VHDL code to simulate the design.
I'm giving a signal assignment to one of the inputs, but my test output on the same channel gives a different value to the one that has been assigned. The circuit and waveform are shown below:
http://img26.imageshack.us/img26/8428/circuits.png
http://imageshack.us/photo/my-images/818/waveform.png/
The two signals i'm referring to are mux_vcc (input) and mux_test (output), which are both connected to the same channel, and can be seen in the schematic. Although in my VHDL code i'm assigning mux_vcc (input) as 0, mux_test (output) is 1 at the very start of the simulation.
I was wondering if someone would please be able to help me out, as one of the purposes of my circuit is to detect the first 1 bit, and this issue means i'm unable to confirm it's performance.
Below is my signal assignments used in VHDL:
Rich (BB code):
mux_vcc <= '0',
'1' after 300 ns;
data_in <= '0',
'1' after 1.142 us,
'0' after 1.213 us,
'1' after 1.283 us,
'1' after 1.354 us,
'0' after 1.425 us,
'0' after 1.496 us,
'1' after 1.567 us,
'0' after 1.638 us,
'1' after 1.709 us,
'1' after 1.780 us,
'0' after 1.850 us,
'1' after 1.921 us;
for i in 1 to num_clk_cycles loop
tran_clock <= not tran_clock;
wait for clk_period/2;
tran_clock <= not tran_clock;
wait for clk_period/2;
Thanks.