Hi
I am trying to simulate a ckt from a research paper using Allegro pspice schematic capture. i am running into a problem when i place current sources in series. current sources with different dc values in series violate KCL.
even with the same current source value for both current sources, Pspice complains that nodes are floating.
how do i resolve this issue ? see attached jpg for more information. the 2 current sources of interest are I5,I6.
any help or thoughts appreciated.
thanks
I am trying to simulate a ckt from a research paper using Allegro pspice schematic capture. i am running into a problem when i place current sources in series. current sources with different dc values in series violate KCL.
even with the same current source value for both current sources, Pspice complains that nodes are floating.
how do i resolve this issue ? see attached jpg for more information. the 2 current sources of interest are I5,I6.
any help or thoughts appreciated.
thanks
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