Alarm for a clock

Discussion in 'General Electronics Chat' started by arthur92710, Feb 28, 2008.

1. arthur92710 Thread Starter Active Member

Jun 25, 2007
307
1
Can some one point me in the right direction for making an alarm for my clocks(both the bcd-binary and 7seg)

I would like that the alarm time is set with a DIP switch set.

I have tried using them but I run into some problems. When you decode 10 min(001-000) it works the 1 goes trough the switch to the transistor and turn on the buzzer. But when you get to 30min(011-0000) the 1 goes thought and turns on the buzzer. It seems like im missing a few gates somewhere but I cant figure out where. For those tests I used only a bcd counter, a Dip switch, a transistor and a buzzer.

2. SgtWookie Expert

Jul 17, 2007
22,201
1,809
You'll need to compare each bit you've set with your DIP switch, with what the current state of the clock counters are.

One way to do that is by using an XOR gate with an inverter, also known as an Exclusive NOR gate, or XNOR.
A 4077 has four 2-input Exclusive NOR gates.

To simplify the explanation, let's look at an Exclusive OR (XOR) gate:
If both inputs are the same (both 1's or both 0's) the XOR output is false (zero).
If the inputs are different (one is 1 and the other is 0), the XOR output is true (one).
If you invert the output of an XOR gate, you get a true when they're the same, and a false when they're different - and you have an XNOR gate.

So you can use an XNOR gate to compare each pair of bits, and use a many-input AND gate to poll all of the outputs of the XNOR gates. When all of the XNOR gates output a true, it's time to wake up. 3. gootee Senior Member

Apr 24, 2007
447
52
EDIT: Sgt. Wookie beat me to it, yet again! Oh well, I'll post this anyway.

I haven't really thought about logic-level stuff for about 25 years. But I'll take a shot at this.

Apparently you don't have enough bits representing your alarm-time setting. You can't look for any single '1' bit, because, as you found out, there are other numbers/bit-patterns for which that bit might also be a 1.

You need to look for an entire particular pattern of ALL of the clock bits, if you want to be able to set any possible desired alarm time.

Say you have a set of switches with one switch for each alarm-time bit, and you want the alarm to be triggered only when every bit for which a switch is set to 'ON' is a 1, and not be triggered for any other bit pattern. That means that the alarm should be triggered only when all of the selected bits are 1, and none of the unselected bits are 1 (i.e. they all must be 0).

Here is the setup for each bit: (This assumes that logic 1 is a positive or negative voltage and logic 0 is 0 volts.)

A SPST (on-off) switch would have one side tied to the logic 1 voltage. The other side would have a resistor to ground (0 volts). Let's call the side with the resistor to ground the "SW" signal. When the switch is open (i.e. "off"), SW is tied to ground through the resistor, and is logic 0. When the switch is closed (i.e. "ON"), the logic 1 voltage is across the resistor and SW is logic 1. So far so good?

According to paragraphs two through four, above: If SW is 1, then the output for that bit should only be 1 if the bit is 1. If SW is 0, then the output for that bit should only be 1 if the bit is 0. For all other cases, the output should be 0.

So basically, for each bit's logic network, we have two inputs (the SW and the bit we're looking at). If both are the same, the output should be 1. If one of them is 1 and the other is 0, the output should be 0.

This could be done with two dual-input AND gates, three dual-input OR gates, and two logic inverters. But there is already a gate that does exactly what is needed. It's the exclusive-NOR gate.

So, for each clock bit, you can just tie that bit's alarm-setting SW and the bit to the inputs of a dual-input exclusive-NOR gate.

Then, all of the XNOR gates' outputs need to be AND'd together. That AND's output will only be 1 when all of the clock bits match the SW settings, which is when you want to trigger the alarm.

Instead of a multi-input AND gate, you could use multiple dual-input ANDs, and cascade them however you want. Actually, you could combine AND gates with any number of inputs each, until you have enough AND inputs.

----------

[Remember that I said I hadn't thought about logic-level stuff for about 25 years. Well, I forgot about exclusive-NOR gates, at first, and solved the problem using only the basic AND and OR gates, and Inverters. I'll post it here for the amusement of Sgt. Wookie. ) ]

<insert paragraphs two through nine, from above>

I'll have one small network of logic gates to handle the case when the bit is logic 1, and another small set of gates to handle the case when the bit is logic 0. Each set has a logic 1 output when the right conditions are met, and both sets' outputs are AND'd, to get that bit's final output, which then goes to the multi-input AND of all of the bits' output states to decide if the alarm should be triggered.

For the case when the bit is 1: the bit and SW go into a dual-input AND gate, which will have output 1 only when both inputs are 1. However, if the SW is 0, we want the other set of gates to make the decision, so we want this set of gates to output 1 whenever SW is 0, no matter what the bit is. Thus, we send the AND gate's output into a dual-input OR gate. The OR gate's other input is from an inverter, with SW as the inverter's input. That way, when SW is 0, it's inverted to 1, and the OR gate will output 1 no matter what the AND gate says. But if SW is 1 it gets inverted to 0, and the OR gate's output will be whatever the AND gate's output is.

For the case when the bit is 0: the bit and SW go into a dual-input OR gate followed by an inverter, which will have output 1 only when both inputs are 0. However, if SW is 1, we want the other set of gates to make the decision, so we want this set of gates to output 1 whenever SW is 1, no matter what the bit is. Thus, we send the inverter's output into a dual-input OR gate. The OR gate's other input is SW. That way, when SW is 1, the OR gate will output 1 no matter what the OR/inverter combo says. But if SW is 0, the OR gate's output will be whatever the OR/inverter combo's output is.

The two final OR gates' outputs go to a dual-input AND gate. The output of that final AND gate is 1 if the bit matches the switch setting, and 0 if the bit does not match the switch setting.

All of the bits' outputs get AND'd together. That output will be 1 if all of the bits match their switch settings, and will be 0 otherwise.

------

- Tom Gootee

http://www.fullnet.com/~tomg/index.html

4. beenthere Retired Moderator

Apr 20, 2004
15,808
295
There is also the 74LS85 magnitude comparitor. It inputs 4 bits from one source and 4 from another, giving outputs for less, equal, and more. A few of them all saying "EQUAL" gives the signal to alarm.

5. nomurphy AAC Fanatic!

Aug 8, 2005
567
13
There's also the 74HC688 comparator.