crutschow showed me a great little AGC circuit, which is found here and described here.

Question 1: Why doesn't the transistor have a base resistor?
Question 2: What needs to be changed in the circuit to make it output another range, say from 0 to 5V?

 

1. I assume you mean the BJT since you said base. I also assume you mean "base resistor" to be a series resistor. It simply isn't needed. The output of the opamp provides a voltage that turns on the BJT when it gets high enough, and sticking a resistor in there wouldn't accomplish anything. Or did you mean something else?
2. You could amplify the output with another opamp. If you're powering it with 5V, you'd need one capable of rail-to-rail output swing.

 

I assume you mean the BJT since you said base. I also assume you mean "base resistor" to be a series resistor.

Both assumptions correct.

It simply isn't needed. The output of the opamp provides a voltage that turns on the BJT when it gets high enough, and sticking a resistor in there wouldn't accomplish anything. Or did you mean something else?

Well, I was thinking about a base protecting (i.e., current limiting) resistor. But I guess because the Op-Amps can't source much current, a base resistor isn't required?

2. You could amplify the output with another opamp. If you're powering it with 5V, you'd need one capable of rail-to-rail output swing.

Ok, what about just 0 to 2V? I.e., why is the limit 0 to 1.2 specifically?

 

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Question 1: Why doesn't the transistor have a base resistor?
Question 2: What needs to be changed in the circuit to make it output another range, say from 0 to 5V?

1: You bring up a good point. Looking at the circuit it would seem that the base-emitter junction would clip the output at the base-emitter voltage of about 0.7V. The output could never get to 1.2V as shown. I believe you do need a resistor in series with the base, but not sure what value. You may have to experimentally try some different values to get the output voltage you want.

2: See the last sentence in answer to 1:

Edit: Correction. OK, I see that the 1.2Vpp corresponds to to a base-emitter peak voltage of about 0.6V since the base emitter just conducts on the peak of the signal. So to increase the output voltage you could add diodes in series with the base. Each diode will increase the PP voltage by about 1.2V. The limit is, of course, the maximum peak output of the op amp.

 

I think Q1 operates around cut-off with its base pulsed with current - effectively the base drive is unipolar differentiator mode topology.

Small changes in the Q1 effective mean bias value then allow suitably large variations in Q1 collector to control Q2's dynamic resistance. C4 in combination with R8 smooths out the effect of pulsations in the Q1 collector current.

 

I've put the circuit together finally. I was struggling with it because of my own mistake (of course). It seems that the capacitors are really polarized. Without them it didn't work. I'm attaching a picture of what the output and input looks like (bottom input, top output). As you can see there's some distortion there. Is that OK for this circuit?

Also, interestingly enough putting the probe on either the collector or the gate of the JFET produces a straight line of 6V (that's my power supply). Is that normal? I was expecting to see a wave of some sort. Or does it mean that that part of the circuit is not working at all?

 

I've put the circuit together finally. I was struggling with it because of my own mistake (of course). It seems that the capacitors are really polarized. Without them it didn't work. I'm attaching a picture of what the output and input looks like (bottom input, top output). As you can see there's some distortion there. Is that OK for this circuit?

Also, interestingly enough putting the probe on either the collector or the gate of the JFET produces a straight line of 6V (that's my power supply). Is that normal? I was expecting to see a wave of some sort. Or does it mean that that part of the circuit is not working at all?

Don't understand you comment about polarized capacitors. Did you put them in backwards? Of course it won't work without the capacitors.

There should be little noticeable distortion. What JFET are you using?

There should be no DC voltage on the drain (JFETs don't have collectors) of the JFET. Sounds like you have a miss-wire or C1 is in backwards. That likely explains the distortion.

 

Don't understand you comment about polarized capacitors. Did you put them in backwards? Of course it won't work without the capacitors.

Lol, I meant I used ceramic non-polarized capacitors instead of electrolytic polarized ones.

What JFET are you using?

J176

There should be no DC voltage on the drain (JFETs don't have collectors) of the JFET. Sounds like you have a miss-wire or C1 is in backwards. That likely explains the distortion.

I thought it was strange as well. But the output voltage does stay at 1.2-1.3V. I'll check tonight.

Thanks!

 

Lol, I meant I used ceramic non-polarized capacitors instead of electrolytic polarized ones.

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I thought it was strange as well. But the output voltage does stay at 1.2-1.3V. I'll check tonight.

Non-polarized caps will work just fine if they are the required capacity (10μF ceramic caps are not common).

The input DC voltage is blocked from the output by C1. Thus there should be no DC voltage on the drain of Q2 since there is no source for the voltage (unless your input has a DC offset).

 

Non-polarized caps will work just fine if they are the required capacity (10μF ceramic caps are not common).

I might have miswired something. It definitely didn't work. Why do they specify polarized caps if it doesn't matter -- just curious?

The input DC voltage is blocked from the output by C1. Thus there should be no DC voltage on the drain of Q2 since there is no source for the voltage (unless your input has a DC offset).

I was talking about the gate of the JFET and the collector of the BJT. But still, the drain is pulled up to the positive rail, doesn't it? Shouldn't it be at the positive rail voltage?

EDIT:

Sorry, it's the gate that is pulled to +V. So, yeah, I was talking about the gate all along. Meaning that I don't see the voltage drop caused by the drop on the collector of the BJT. I must have messed up somewhere. I've checked the circuit a 100 times though -- will do again.

 

The base of Q1 conducts when the peaks exceed ≈0.6V. These current pulses briefly turn on the transistor, causing collector current impulses. These impulses are filtered by C4, decreasing the gate voltage on the pjfet, causing its on resistance to decrease until it reduces the gain to the point where the p-p voltage at the output is 1.2V (0.6V peak).
You don't need a base resistor. It would just make the AGC sloppy (less constant amplitude).

 

These impulses are filtered by C4, decreasing the gate voltage on the pjfet

Can you explain why exactly we need the C4? If we remove it completely and break the connection to ground, won't it work the same?

Also, I couldn't find 240K resistors. I used 220s, is that OK?

 

Can you explain why exactly we need the C4? If we remove it completely and break the connection to ground, won't it work the same?

Also, I couldn't find 240K resistors. I used 220s, is that OK?

Without C4, you will get 5V pulses on the pjfet gate. You want a voltage with as little ripple as possible there.
220k resistors are fine.

 

Without C4, you will get 5V pulses on the pjfet gate. You want a voltage with as little ripple as possible there. 220k resistors are fine.

Ok. What's the best way to test if the JFET + BJT part is working? The BJT collector voltage should change periodically and I should catch it with a scope -- is that right?

 

Ok. What's the best way to test if the JFET + BJT part is working? The BJT collector voltage should change periodically and I should catch it with a scope -- is that right?

It won't work unless you build the entire circuit. The way to test it is to apply an input with varying amplitudes, and see if the output level is relatively constant. The proof of the pudding, so to speak.
The collector voltage on the BJT should go down as the input amplitude is increased. It won't change periodically unless you change the input amplitude periodically.

 

I might have miswired something. It definitely didn't work. Why do they specify polarized caps if it doesn't matter -- just curious?
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I was talking about the gate of the JFET and the collector of the BJT. But still, the drain is pulled up to the positive rail, doesn't it? Shouldn't it be at the positive rail voltage?

EDIT:

Sorry, it's the gate that is pulled to +V. So, yeah, I was talking about the gate all along. Meaning that I don't see the voltage drop caused by the drop on the collector of the BJT. I must have messed up somewhere. I've checked the circuit a 100 times though -- will do again.

They don't specify polarized capacitors because they are required, it's just that most capacitors above about 1μF or so are usually electrolytic types which are all polarized by their nature (but it's not particularly desired).

If the FET gate is at 6V (where it would be with a low or no input) then it should be cut off and your circuit should be delivering maximum gain (as if the FET weren't there).

 

Ok. What's the best way to test if the JFET + BJT part is working? The BJT collector voltage should change periodically and I should catch it with a scope -- is that right?

You might see a small blip but the capacitor is there to smooth the voltage change to it remains at near DC.

 

It won't work unless you build the entire circuit. The way to test it is to apply an input with varying amplitudes, and see if the output level is relatively constant. The proof of the pudding, so to speak.

Finally started working correctly yesterday. After checking and re-checking everything, I noticed that once the pot was removed the distortion was gone. After an hour of scratching my head, I decided to put the 10K (R7) resistor in. And it did it. The output is completely fine now. crutschow said 10K was not essential, so I left it out. But without it and the pot in, there's distortion. There's always a possibility I messed something else up of course! crutschow, I'm not complaining or trying to disrespect you at all -- just recounting what happened.

The collector voltage on the BJT should go down as the input amplitude is increased. It won't change periodically unless you change the input amplitude periodically.

You guys are so freaking good. Unbelievable. Hat's off to you all.

One simple question: so now I have the output from the AGC. The circuit that actually analyzes the frequencies is on another breadboard controlled by an arduino and powered by it. How do I interface them together correctly?

I.e., would it be correct to just connect the output of the AGC to the input of the equalizer chip (which is on the arduino breadboard) and connect the ground from the AGC breadboard to the ground of the arduino breadboard?

 

Finally started working correctly yesterday. After checking and re-checking everything, I noticed that once the pot was removed the distortion was gone. After an hour of scratching my head, I decided to put the 10K (R7) resistor in. And it did it. The output is completely fine now. crutschow said 10K was not essential, so I left it out. But without it and the pot in, there's distortion. There's always a possibility I messed something else up of course! crutschow, I'm not complaining or trying to disrespect you at all -- just recounting what happened.

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One simple question: so now I have the output from the AGC. The circuit that actually analyzes the frequencies is on another breadboard controlled by an arduino and powered by it. How do I interface them together correctly?

I.e., would it be correct to just connect the output of the AGC to the input of the equalizer chip (which is on the arduino breadboard) and connect the ground from the AGC breadboard to the ground of the arduino breadboard?

Still don't see why the 10kΩ output resistor is needed. Perhaps it's some quirk of the op amp. But certainly the pot is needed to provide a source for the negative charge to C1 to match the positive charge going into the base of Q1.

Yes, just connecting the two grounds together should work.

 

Still don't see why the 10kΩ output resistor is needed. Perhaps it's some quirk of the op amp.

Yes, just connecting the two grounds together should work.

The datasheet recommends a 10k pulldown on the output to get it to go within a few millivolts of the negative rail, and to eliminate crossover distortion.
"For ac applications, where the load is capacitively coupled to the output of the amplifier, a resistor should be used, from the output of the amplifier to ground to increase the class A bias current and prevent crossover distortion. Where the load is directly coupled, as in dc applications, there is no crossover distortion."

But certainly the pot is needed to provide a source for the negative charge to C1 to match the positive charge going into the base of Q1.

I agree with this.