Adding SDRAM to a project

Discussion in 'Embedded Systems and Microcontrollers' started by Jorgy, Nov 21, 2009.

  1. Jorgy

    Thread Starter New Member

    Oct 10, 2009
    Hey Everyone,

    I am using a Virtex II Pro and I am trying to start a new project and use the SDRAM as my memory for Instruction, Data, and Stack/Heap sections for the Peripheral Test. I currently just have the default source code that was in TestApp_Peripheral.c file that gives the status of the GPIO input and output, but when I download the Bitstream to the FPGA I am not getting any output out of Hyperterminal. Is there anything I have to change in order to make the SDRAM my default memory or to give me an output?