Hello

I am trying to play with this circuit (attached image) in Yenka (a circuit simulator), but it's not doing what I expect it to.

As I understand it, this circuit should take two binary numbers, each 2 bits, and add them together, giving a three bit output. Is this what an adder is supposed to do?

The circuit works if all 4 inputs are brought high. The circuit rightly calculates that 1+2+1+2 = 2+4, but other permuations don't seem right, like 1+0+0+0 = 2.

I found the circuit image through Google, which lead me to a forum where another person was asking for help with the image, but never got a response. Is the circuit therefore incorrect?

Thanks in advance.

 

Have a look here:
http://en.wikipedia.org/wiki/Adder_(electronics)

 

I've had a look at a truth table listed there, and I'm now sure what an adder is for. What I'm after is a logic gate equivalent of the 74HC83 chip (But I'd only be using A1,A2,B1 and B2, not the 4 or 8 inputs). None of the circuits I found on the internet seem to work when I try them. I've written up an overall truth table for what I want, and am trying to figure out a circuit that will satisfy the truth table, but any circuits you know of would do too.

Thanks

 

If you look at the datasheet for the 74HC83, you will see an "Equivalent Circuit" that shows the circuit "inside" the chip.

You can copy that.

 

I have the circuit here, and there seem to be a few oddities with it, can you explain them please?
For example, here

There is a NOR with inverted output, why not just an OR? Same with the NAND. In fact, on closer inspection, the NOR/OR appears to have both inputs inverted too. Why not use a NAND?
The other oddity is here:

With three NOTs in a row.


The only thing I can think of is that this circuit is literally what is inside the chip, and the manufacturer had to design the die that way for some reason (space?).

Anyways, I can probably simplify this circuit some. Thank you a lot

 

I have the circuit here, and there seem to be a few oddities with it, can you explain them please?
For example, here

There is a NOR with inverted output, why not just an OR? Same with the NAND. In fact, on closer inspection, the NOR/OR appears to have both inputs inverted too. Why not use a NAND?
The other oddity is here:

With three NOTs in a row.


The only thing I can think of is that this circuit is literally what is inside the chip, and the manufacturer had to design the die that way for some reason (space?).

Anyways, I can probably simplify this circuit some. Thank you a lot

You are on the right track. In CMOS ICs, an AND gate is made with a NAND followed by an inverter.
The three inverters are probably for propagation delay matching (with the other outputs), and possibly to scale the device sizes up so the output drive specs are met.