add and subtract two 4-bit binary numbers using verilog

Thread Starter


Joined Dec 28, 2012
hey every one

I'm new here as a member but I'm watching you for a long time

I have a project to do in verilog which is a hardware description language (program ) (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits.

and here is my project :

Design a digital logic circuit and prototype your design on the Nexys2 board (available at the EE store or with the instructor) that will show the result on a seven-segment display of the hexadecimal value for the following operations:
1. The sum of two 4-bit binary numbers A and B
2. The subtraction of B from A using two’s complement addition
3. The value of A and B
4. The value of A or B

The four pushbuttons on the Nexys2 board are to be used to determine which one of the four values listed above is displayed. All values are to be displayed as hexadecimal numbers and no indication of overflow is necessary. The following information describes the specification for displaying the values:

• No Buttons pressed – Blank Display
• BTN0 – The sum of two 4-bit binary numbers A and B
• BTN1 – The subtraction of B from A
• BTN2 – A & B (bit-by-bit Boolean and operation)
• BTN3 – A | B (bit-by-bit Boolean or operation)

If more than one pushbutton is pressed at a time, then set the display based on the highest numbered button that is pressed. For example, if BTN0 and BTN2 are both pressed, then display the value of A&B. If no buttons are pressed, the display should be blank.

The four leftmost switches (SW7 – SW4) on the Nexys2 board shall represent the values for A.
The four rightmost switches (SW3 – SW0) shall represent the values for B.
You may ignore any results due to arithmetic overflow.

i think for the first one we use 4 full adders and for the second one we ues 4 binary subtractor , am i right ?

I hope that you can help me to do it in verilog because i don't have any idea about it and i don't have time to learn how to use verilog because i have finals these days.

thanks ,