Hello Everyone!

I have a little problem with converting data with ADC0804
i wrote a state machine in VHDL that will do the conversion but it's not working as i expected, maybe someone can help me, and show his state machine in VHDL and the schematics of the pin connection it's very urgent, for my graduate design

for analog input i'm using LM35 with UA741 to amplify the signal
and DE2 with CycloneII the FPGA component

thank's

 

Maybe you can show some of your design with some supporting documents as to why you did it first...

What part of the design is not working?

 

i think that my vhdl code for the state machine is not working correctly
i can show it here: if any one of you can see what the problem and correct it i'll be thankful

library ieee;
use ieee.std_logic_1164.all;

Entity A_TO_D is
port( INTR,clk:in std_logic;
--Bitdata:in std_logic_vector(7 downto 0);
CS,WR,RDut std_logic--chip select,write,read
);
end A_TO_D;
architecture state_a_d of A_TO_D is
type state_type is (s1,s2,s3,s4,s5,s6,s7);--name of states
signal css, NS:state_type;--current state & Next state
begin
process(css)
begin
case NS is
when s1=> CS<='1';
WR<='0';
--INTR<='0';
NS<=s2;
when s2=> CS<='1';
WR<='1';
--INTR<='0';
NS<=s3;
when s3=> CS<='1';
WR<='0';
--INTR<='0';
NS<=s4;
when s4=> CS<='0';
WR<='0';
--INTR<='0';
NS<=S5;
when s5=> CS<='0';
WR<='0';
if (INTR='1') then NS<=s6;
else
NS<=s5;
end if;
when s6=> CS<='1';
RD<='0';
if (INTR='1') then NS<=s7;
else
NS<=s6;
end if;
when s7=> CS<='1';
RD<='1';
if (INTR<='1') then NS<=s1;
else
NS<=s1;
end if;
end case;
end process;
clprrocess(clk)
begin
if (clk='1' and clk'event) then
css<=ns;
end if;
end process;
end state_a_d;

 

and of course i used the time diagram that shown in the pdf file that i've attached in pages 6&7
thank's

 

A little help from someone?

 

I think you need to look at the timing diagrams again. If I look at your first state, it looks like you are setting the chip select, CS, to '1' and the write line, WR, to '0'. I don't see that case anywhere in the diagrams. The CS always goes low before either the WR or RD lines.

How are you clocking the state machine? Are you meeting the timing requirements of the diagrams? I see you have a CLK and every rising edge changes state, but how are you creating CLK to meet the timing requirements?

 

well first of all thank you for your reply
if you can see in the data sheet(page 11 for example) i can connect to "CLK IN" and "CLK R" capacitor=150pf, and a resistor=10k and that will make a clock of f=606KHz(there is a formula in page 23) and that will be my clocking
but if you wrote a code for ADC0804 with a VHDL Code i'll be glad ful if you'll show it to me
thank's

 

I have not written code for the ADC0804.