Adc

Thread Starter

tosameena

Joined Aug 22, 2007
8
hi all,

i have written a code for ADC in VHDL..
the problem is with the type syntax..

Type state(s0,s1,s2,s3,s4,s5,s6,s7) is std_logic_vector (3 downto 0);
type state is array(3 downto 0) of std_logic_vector;

im getting error stating that s0 to s7 is not declared....

can you please help me out in correcting it...

thank you
 

Dave

Joined Nov 17, 2003
6,970
To start with have you put:

Rich (BB code):
library ieee;
use ieee.std_logic_1164.all;
At the start of the code?

Dave
 
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