hi all,
i have written a code for ADC in VHDL..
the problem is with the type syntax..
Type state(s0,s1,s2,s3,s4,s5,s6,s7) is std_logic_vector (3 downto 0);
type state is array(3 downto 0) of std_logic_vector;
im getting error stating that s0 to s7 is not declared....
can you please help me out in correcting it...
thank you
i have written a code for ADC in VHDL..
the problem is with the type syntax..
Type state(s0,s1,s2,s3,s4,s5,s6,s7) is std_logic_vector (3 downto 0);
type state is array(3 downto 0) of std_logic_vector;
im getting error stating that s0 to s7 is not declared....
can you please help me out in correcting it...
thank you