I know what drives the N-bit choice of a ADC/DAC but what drives the samples per second spec on an Analog to Digital Converter?

Thinking about using a AD7680. It's a 16-bit 100 kSPS ADC. An input range of zero to about 5.5 volts and the highest frequency of 2200 Hz.

 

It is the SCLK input the drives the conversion. 1 conversion takes 20 SCLK cycles. You can use 2.5 MHz as max SCLK frequency and 250KHz as min frequency.

 

You can use 2.5 MHz as max SCLK frequency and 250KHz as min frequency.

Did you take this from the datasheet?

Thanks for the reply.

 

Yes it is all in the data sheet

 

Yes it is all in the data sheet

What if the CLK speed is much higher?

 

The clock speed, is specified by the manufacturer. So going outside these limits will produce erratic errors. I can not give you a more precise answer than that

 

It is the SCLK input the drives the conversion. 1 conversion takes 20 SCLK cycles. You can use 2.5 MHz as max SCLK frequency and 250KHz as min frequency.

According to the datasheet, SCLK minimum is 10kHz.

 

Not as I read it. But anyway the OP wanted the fast samplerate so it does not matter.

 

What are you trying to sample?

 

Not as I read it. But anyway the OP wanted the fast samplerate so it does not matter.

Turns out I was looking at a preliminary datasheet from datasheetcatalog.org.

 

What are you trying to sample?

A 4-20 mA with HART Comm (1 mA peak to peak) riding on top of it at a maximum frequency of 2200 Hz running through a 250 Ohm sense resistor.

 

2200Hz or 2200MHz? thats a huge difference

 

2200Hz or 2200MHz? thats a huge difference

Sorry about that. It's suppose to read 2200 Hz.