Thanks,
while reading a paper on digital Calibration and Testtime Reduction on ADC i came across the following line :-
" longer test sequence required to accumulate sufficient information about circuit non idealities result in longer calibration time for digitally calibrated devices."
Can you please tell what is the meaning of CIRCUIT NON IDEALITIES?
For example the response could be slightly off from linear, so if you draw a line between the top and bottom values, the ones in the middle could be a bit off. Other things could be noise and stability of the readings.
The two major CIRCUIT NON IDEALITIES are offset voltage and gain errors.
One can perform a digital calibration by applying a known very small and a known very large input signal. By assuming a linear response*, and using the ADC output along with these two known points the transfer function can be computed.