# accessing of external code memory

#### bleach118

Joined Dec 4, 2008
15
can u please explain me how the accessing of external code memory happen with graph if possible. in μc 8051

thanks

#### beenthere

Joined Apr 20, 2004
15,819
An 8051 has 16 address lines and 8 data lines. By following the data sheet for the 8051 and the memory IC, you will be able to access the data. The data sheet for the external memory will have the timing chart (possibly what you meant by "graph") included.

If it is a modern variant of an 8051, then the uC may be able to use serial memory. Again, the data sheet for the memory chip will have all the necessary interfacing information in it.

#### Papabravo

Joined Feb 24, 2006
19,558
To expand on the previous post. There are two potential types of external memory.
1. Code Memory, which contains instructions and is accessed with the signal PSEN-bar. PSEN stands fro Program Store ENable. The code memory or progream store is read-only. There is no write strobe for it.
2. Data Memory, which contains data and is accessed only with the MOVX instruction. There are two forms of the MOVX instruction depending on how many address bits you intend to use.
Rich (BB code):
      MOVX A,@DPTR      ; External Read, 16-bit address, RD* active
MOVX A,@Ri        ; External Read, 8 -bit address, RD* active, for i = {0,1}

MOVX @DPTR,A      ; External Write, 16-bit address, WR* active
MOVX @Ri,A        ; External Write, 8-bit address, WR* active, for i = {0,1}

#### bleach118

Joined Dec 4, 2008
15
a cording to the figure of accessing external data memory i want to understand how the things happen in short and simple way. like when the address coming from port 0 is low and it go to latch circuit, and the high byte address from port 2 go directly to external Ram .. etc
the logic is confusing me and i can't put it in proper way

#### bleach118

Joined Dec 4, 2008
15
i am trying to put the interface to external Ram figure but i don't know this URL things

thanks

#### bleach118

Joined Dec 4, 2008
15

#### bleach118

Joined Dec 4, 2008
15

#### Papabravo

Joined Feb 24, 2006
19,558
OK, so external data RAM
1. High order address bits go on P2. They are valid from the beginning of the memory cycle to the end of the memory cycle.
2. P0 has low order address bits at the beginning of the cycle, and either "read" data or "write" data at the end of the cycle.
3. The signal ALE (Address Latch Enable) is high when P0 contains address bits. The falling edge of ALE allows a device called a transparent latch to capture the value of the P0 address bits at their value a short time (several nanoseconds) before the falling edge of ALE. This is called a setup time.
4. Some time after the falling edge of ALE, either RD* or WR* will go low. This tells the external RAM device if the operation is going to be a READ or a WRITE. When the rising edge of RD* happens the external RAM must have placed a byte of data on the P0 data bus. In a WRITE cycle the processor must have placed a byte of data on the P0 data bus to be written.
If the current cycle is not an external memory reference cycle then neither RD* nor WR* will go active(low) and the external RAM will neither read nor write any data. Only the MOVX instuctions can produce an external memory cycle. All other instructions are internal.

It is possible to fetch instructions from external code memory using the same addressing mechanism used for external data read, but using PSEN* instead of RD*. Some designers combine RD* and PSEN* with an AND (74xx08) gate to produce a single READ strobe for a common code and data memory. The deMorganized expression is RD* low OR PSEN* low gives READ Strobe low.

#### bleach118

Joined Dec 4, 2008
15
thanks

The falling edge of ALE allows a device called a transparent latch to capture the value of the P0 address bits at their value a short time (several nanoseconds) before the falling edge of ALE. This is called a setup time.
can u please explain me this part.......

When the rising edge of RD* happens the external RAM must have placed a byte of data on the P0 data bus. In a WRITE cycle the processor must have placed a byte of data on the P0 data bus to be written.
how i tell that if it is read or write process?

if i am having external ram and eternal ROM can i use them at the same time or i must use one of them at the time...

thanks alot

#### Papabravo

Joined Feb 24, 2006
19,558
ALE goes to the enable of a transparent latch such as a 74xx373 or 74xx573. When ALE goes high the data from P0, connected to the inputs of the transparent latch flows through to the outputs of the transparent latch. When ALE falls (goes low) the values on the inputs a few nanoseconds before the falling edge are preserved on the outputs of the transparent latch regardless of what the inputs do after the falling edge of ALE.

In an external data memory access, either RD* will go low or WR* will go low. They cannot both go low on the same cycle. It is of course the case, most of the time, that neither one will go low. This means that the current instruction is NOT doing a READ or WRITE to external memory. All of this information is in the datasheets and the hardware manuals, I don't understand why this is so difficult for you. Is this your first experience with a processor bus?

You can have both an external ROM and an external RAM. The OE* pin on the ROM is connected to PSEN* (as I've mentioned at least three times previously). The OE* pin on the RAM goes to RD* on the processor. The WE* pin on the RAM goes to WR* on the processor. You probably need for the EA* pin on the processor to be low as well.

How you generate chip select for the external ROM and the external RAM depends on the respective memory sizes contained in the chips. In both cases the high order address lines come from P2 and the low order address lines come from the output of the tranparent latch.

#### bleach118

Joined Dec 4, 2008
15
In an external data memory access, either RD* will go low or WR* will go low. They cannot both go low on the same cycle. It is of course the case, most of the time, that neither one will go low. This means that the current instruction is NOT doing a READ or WRITE to external memory. All of this information is in the datasheets and the hardware manuals,
I don't understand why this is so difficult for you. Is this your first experience with a processor bus?
Yes, this my first time, actually it is in micro controller.
am really confused but still am welling to learn, so i will keep trying

thanks