This is a graphical construction used to estimate collector-emitter voltage Vce and collector current Ic in a transistor amplifier. The example appears to be for an NPN common-emitter amplifier with a capacitively coupled external load.I'm talking about the line shown on this graph. I don't understand what your talking about.
Can you supply the schematic of the transistor amplifier circuit that goes with the plot?I'm talking about the line shown on this graph. I don't understand what your talking about.
by Jake Hertz
by Duane Benson
by Duane Benson
by Jake Hertz