# A question about digital memory

#### IsquaredC

Joined Nov 28, 2011
3
How many bits exactly are being addressed for each size of memory? For example, if I had a static RAM that was like, 256 x 8 bits, I understand that the memory would have 256 addresses and 8 data busses, but does that also mean that 8 actual bits are being stored in each address? If so, you'd only be able to store 4 bits per address in a 256 x 4 RAM and 12 bits per address in a 256 x 12 RAM? Is that how it works? Because the brief explanation in the online text was kind of confusing...

#### thatoneguy

Joined Feb 19, 2009
6,359
256x8

You have 256 addresses, each of which will return 8 bytes.

To store a single bit, you'd need a 1024x1 RAM array, less than 256 single bits to store as bytes, or you'd need to start with creative post-fetch masking so you know which bit from which address is the one of the 1024 you are looking for.

If the memory was addressable down to byte size in a PC, there would simply be too many address lines to fit, not to mention the extra time taken to return a 32bit word.

#### spinnaker

Joined Oct 29, 2009
7,835
256x8

You have 256 addresses, each of which will return 8 bytes.

To store a single bit, you'd need a 1024x1 RAM array, less than 256 single bits to store as bytes, or you'd need to start with creative post-fetch masking so you know which bit from which address is the one of the 1024 you are looking for.

If the memory was addressable down to byte size in a PC, there would simply be too many address lines to fit, not to mention the extra time taken to return a 32bit word.
Sorry for hijacking the thread but the OP hit on a very interesting subject. One of which i think many people do not fully understand including me. Are you aware of any sites that explain this technique but not get bogged down in the fine details?

#### MrChips

Joined Oct 2, 2009
21,880
How many bits exactly are being addressed for each size of memory? For example, if I had a static RAM that was like, 256 x 8 bits, I understand that the memory would have 256 addresses and 8 data busses, but does that also mean that 8 actual bits are being stored in each address? If so, you'd only be able to store 4 bits per address in a 256 x 4 RAM and 12 bits per address in a 256 x 12 RAM? Is that how it works? Because the brief explanation in the online text was kind of confusing...
You are correct.

#### thatoneguy

Joined Feb 19, 2009
6,359
Sorry for hijacking the thread but the OP hit on a very interesting subject. One of which i think many people do not fully understand including me. Are you aware of any sites that explain this technique but not get bogged down in the fine details?
Which technique?

You are VERY familiar with reading/setting the state of a bit from a byte in a TRIS or STATUS port.

When working with larger memory and larger amounts of data, such as in a 32 or 64 bit PC, the data is transferred 32 or 64 bits at a time, as quickly as possible. The memory bandwidth is holding back speeds right now, which is why more cores with much more cache are added to CPUs in PCs to be faster, even when running at the same clock speed. Then the word or double word of data can be processed much quicker by ignoring the parts it wasn't looking for, while saving that entire block in the CPU cache. If the block is modified, it is either written back later or discarded by complex algorithms implemented by another processor called the cache controller, which ties together the actions of all the CPU cores with DRAM.

A modern CPU has at least 2 caches, one per core, and one pool that all cores access., Due to the looping nature of programs, some memory is cycled through many times before the final result is written to memory. Since the SRAM cache is way faster than the DRAM main memory, the cache controller and CPU cores along with the pipeline optimizing pre-processing of instructions make this process so as few as possible fetches and writes to DRAM are made.

Does that help?

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#### thatoneguy

Joined Feb 19, 2009
6,359
Instead of editing, I'll expand my first post.

1k of memory can be stored as:

1024 x 1 bits: 1024 address lines with 1 bit I/O line
256 x 4 bits: 256 address lines with 4 bit I/O lines
32 x 32: 32 address lines with 32 bit I/O lines

And so on..

There's only so many pins on a memory module, DIMMS used in today's CPUs use a bunch of BGA DRAM chips on a board with a DRAM controller (which is part of the board chipset on PCs), so that only address and I/O lines are needed. The RAM controller on the DIMM decides how the BGA DRAM chips are presented to the computer, e.g. 32 bit word or 64 bit, the motherboard BIOS can change this based on the processor installed if the board is capable of full 64 bit operation. For a 2GB RAM DIMM, you have 64 lines of I/O, either single or double word, the rest of the pins are telling the memory controller on the DIMM which double words from RAM are being requested. This is a slow process, compared to the speed that the CPU and direct linked SRAM operate.

There is also the problem of c, signals can only get from the DIMM to the CPU as fast as electricity can travel through copper, and we are at that limit. You'll notice if you look at a motherboard from a decade ago, that memory was quite a bit further from the CPU as it is today, and that isn't just so it looks cool. It's thermally bad, since the 4 most thermally active components (CPU Power, Board Chipset, CPU, Memory) must be put into a small space rather than spread out for more even cooling. Needs Must

#### Wendy

Joined Mar 24, 2008
22,164
Older PCs used smaller sizes. The old 8 bit CPUs were just that, 8 bits per word. The address line was 16 bits (which is 2X8 bits, 65535 total memory).

I have a garage full of older PCs. Want one?

#### bertus

Joined Apr 5, 2008
20,773
Hello,

There are different types of RAM.
You have the SRAM (static Random Access Merory),
These are like flip-flops that keep the information without refresh, until the power is cut.

And the DRAM (Dynamic Random Access Memory),
These are like little capacitors that hold the data.
This type of memory needs to be refreshed in a certain cyclus.
Without the resfresh the data will get altered.
Also here the data is kept as long as the refresh is there and the power is there.

http://en.wikipedia.org/wiki/Random-access_memory

Bertus

#### thatoneguy

Joined Feb 19, 2009
6,359
Older PCs used smaller sizes. The old 8 bit CPUs were just that, 8 bits per word. The address line was 16 bits (which is 2X8 bits, 65535 total memory).

I have a garage full of older PCs. Want one?
I remember "upgrading" my RAM from 256k to 512k. That was a LOT of DIPs to be plugged in. Back then, memory used to go bad, too. What a nightmare, especially with the price of RAM. I remember letting a computer run a memory test for a week to find out which address was bad, then another couple days for an answer on a BBS to find out which chip on the motherboard that address was.

Sometimes, the good old days weren't.

#### IsquaredC

Joined Nov 28, 2011
3
Awesome responses! I think I understand this naming system much more clearly now.

#### spinnaker

Joined Oct 29, 2009
7,835
Hello,

There are different types of RAM.
You have the SRAM (static Random Access Merory),
These are like flip-flops that keep the information without refresh, until the power is cut.

And the DRAM (Dynamic Random Access Memory),
These are like little capacitors that hold the data.
This type of memory needs to be refreshed in a certain cyclus.
Without the resfresh the data will get altered.
Also here the data is kept as long as the refresh is there and the power is there.

http://en.wikipedia.org/wiki/Random-access_memory

Bertus
Not to mention core memory. I used to work on a SEC 11/02 based system. It had a whopping 32K of RAM and had to be loaded by magnetic tape. It would take forever to load.

We had a customer in NJ that had magnetic core. They could have their system shutdown for a week. I could walk in, fix what I needed to fix, power on the system and get it up and running off of the core alone.

BTW the 32k included code + the database for a security / fire system.

Kind of scary that they would leave it shutdown for that long. But it gets worse. One customer was a prison in Montreal. They would shut down the system so they could have enough power to do the laundry.

This system had crystal filters that were very sensitive. The prison was always breaking those crystals and I could never figure out way till when during a site visit an alarm came in and the system stated to shake like a hula dancer. They had the TTY on top of the system and it was shaking the heck out of it.

#### thatoneguy

Joined Feb 19, 2009
6,359
On the topic of memory refresh in DRAM, if you are raided by the Feds, and computer information is suspect, they will cryogenically freeze the motherboard, where the contents of RAM can be read out up to several hours later. Combined with the literally frozen CPU, they can deconstruct exactly what programs were running before the system was reset or powered down.

Same goes for Hard drive writes. They can re-construct the last 3 or so sets of data that occupied the platter to recover information that was overwritten. Difference is, the drives don't need to be instantly frozen. This is why a program such as dban is used in secure systems (banks, DoD, etc) to overwrite a drive with random numbers 5 times before being thrown into the mechanical shredder.

Hard drive manufacturers have actually embraced this technology (except the physical shredding part), and given us quad+ capacity drives by using multiple field strengths. This is similar to the boost from 2400 baud to 9600 baud boost that quadrature encoding gave modems, quadrature fields on layers have massively increased Hard Drive storage in the past 4-5 years.