While studying logic design, I have discovered a simple logic circuit that seems to have a unique property. The idea behind this design is based on simplicity similar to what one can find in RISC processors.
This Logic circuit is a grid of NAND gates interconnected in a simple fashion. In the following diagrams:

In these diagrams first the symbol for NAND gates is slightly altered for ease of drawing. Consider an ordinary NAND gate which has two inputs from left and an output to the right. Then add another output and represent the NAND gate by a square. The inputs to this NAND gate come from the top and the bottom of the gate and outputs go to the right and left. The bubbles designate the outputs of the NAND gate. For the next NAND gate, rotate the previous one 90 degrees so that the outputs of the second NAND gate are on the right and left and the inputs are the top and bottom. Now connect the NAND gates and continue the process in a checkerboard matrix fashion (black and white cells). In this arrangement, each output feeds an input.
I have discovered hat any such matrix of any dimension is monostable. Because the signal loops through several paths, such circuits are usually unstable (bistable). But for reasons that I do not fully understand, this circuit of NAND gates is monostable regardless of its dimensions.
I do not know if this circuit has any practical application or it is simply a finding in Logic. Any thoughts on this issue are appreciated. Thanks in advance.

 

Is this mono in reality or simulation or BOTH?

What particular manufacturer and model did you use?

 

I know VERY little about electronics logic, but if I had to venture a guess, I'd say it's monostable because of the feedback.

Once it gets set to one state it is constantly fed throughout the matrix until reset.

 

Monostability of this circuit was verified some years ago by making a simple circuit using ordinary 7400 NAND gates. It has also been tested with a turbo Pascal simulation program I wrote specially for this circuit. After I verified that the program was working, I put it in a loop and it showed monostability in hundreds of thousands of tries with no exception.

I have attached the program and the source code in a zip file called "lattice.zip". This is an MS-Dos program. The output of each NAND gate is represented by 1 or 0. The horizontal signal flow is shown with these signs "<",">". The vertical signal flow is outward from the NAND gate when the horizontal signal flow is inward and vice versa (please refer to the figure). Please note that for ease of programming, this simulation only works with square matrix of NAND gates with even number of NANDs on each side. Also in this simulation, the number of NAND gates on each side is limited to 30.

 

User WannaBinventor sade: it's monostable because of the feedback. Once it gets set to one state it is constantly fed throughout the matrix until reset.

Actually this circuit has memory. It works like a asynchronous state machine. And the bigger the matrix is, the more states it has.