pls help..
i need to build a 9 to o down counter using d flip flop. i'm just a newbie, so i have no idea where to start...

 

An actual circuit? Or just design the logic gates? How many bits? Are you going to implement the design on a board? - Going to need a little bit more info chief haha.

 

This is a common exercise in an introductory course on digital logic sequential design.

There are three steps:

1. Draw the truth table of current state and next state.
2. Draw Karnaugh maps for each flip-flop.
3. Implement combinational logic for specific type of flip-flop used.

You can pick up the steps here:

http://forum.allaboutcircuits.com/showthread.php?t=58572

 

oh i'm sorry. yeah, i need to put it on PCB. it's 9 to zero so four bits, XD

 

is my truth table correct?


DCBA DCBA(next state)
1111 xxxx
1110
1101
1100
1011
1010 xxxx
1001 1000
1000 0111
0111 ...
0110
0101
0100
0011
0010
0001 ...
0000 1001

 

No.

In the left column, list all possible states, 0000 - 1111, in order.
In the right column, list the state that follows from the current state (in left column).
If the current state does not exist, put XXXX in the right side column.

DCBA DCBA(next state)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

 

You may find the following threads for an eBook submission useful:

Synchronous Counters

Modulus Counters

 

I'm sorry, I thought it should be like that since i'm counting down. XD

Sir, I've done it already and also the kmap. this is what i've got.
for A: D'
for B: CD' + A'C'D
for C: BC' + BD' + B'CD
for D: AD' + BCD


is it correct? how am i going to implement it on the d flip flop? thank you so much.

 

argh, someone told me i should make the truth table from nine. but i already did the 0-9. i'm in a bind now.

 

It does not matter what order you create the truth table. The order can be totally random, so long as you include all of the states, used or not used.

It is simply straight forward to go from 0 to 15 so that you do not miss a state.

My results of the Karnaugh maps do not match your expressions you have shown.

 

then here's my truth table..

DCBA DCBA(next state)
0000 0001
0001 0010
0010 0011
0011 0100
0100 0101
0101 0110
0110 0111
0111 1000
1000 1001
1001 0000
1010 xxxx
1011 xxxx
1100 xxxx
1101 xxxx
1110 xxxx
1111 xxxx

i did kmap again and still arrived at the same results.

 

You have shown a count up sequence 0-9.
I thought you needed count down 9-0.

 

ahh.. i get it. sorry.

A: D
B: C'D' + A'D + B'CD
C: B'D' + A'D + B'C'D
D: A'D' + ABCD


is it correct? thanks again.

 

ahh.. i get it. sorry.

A: D
B: C'D' + A'D + B'CD
C: B'D' + A'D + B'C'D
D: A'D' + ABCD


is it correct? thanks again.

In general, we need to see HOW you arrived at a result and not just the result you arrived at. Our goal is to help you understand how to solve a problem, not just confirm or deny that your result is correct.

One of the nice things about most engineering disciplines is that you can verify the validity of a result from the result itself. You don't need to (and need to learn not to) rely on others to tell you if you are correct or not.

So take your solution and then analyze the behavior of the circuit that results. If it matches the behavior that you want, then it is correct. Otherwise, it ain't.

QD|QC|QB|QA||DD|DC|DB|DA||QD'|QC'|QB'|QA'|Description
0|0|0|0||1|1|1|0||1|1|1|0|0 => 12

Already we can see that the equations you came up with will NOT result in the behavior you want.

So how about showing the K-map for one of the stages, say the first one or the last one, so that we can see how you arrived at the equation you did?

 

i didn't get the table, sorry.

 

i didn't get the table, sorry.

If you are referring to the table in my last post, then it is nothing more than the start of a state transistion table.

I chose (0000) as the starting state for the four Q outputs.
I then used your proposed equations to find the values of the four D inputs.
I then applied the inputs to find the next set of four Q outputs.
I then noted the numeric values associated with this transistion.

Since you want 0->9 and not 0->12, there is a problem.