I never heard of Gaonkar, never read it. I always start with the manufacturers datasheets.
- Program memory must be present at address 0x0000 because that is where the porcessor goes to start fetching instructions after RESET_IN* (pin 36) is released. I believe that if there is no memory at location 0x0000 that the data buss will return an 0xFF which is an RST 7 instruction. This will then go to locatio 0x0038 with predictable results.
- Just put the proper return instruction at the appropriate location, or tie the TRAP (pin 6) high or low as appropriate so that a TRAP condition never occurs.
- The HOLD (pin 39) and HLDA (pin 38) are used to request bus mastership. The hold state will not be released until HOLD goes low.
Don't know if they are still available on the Intel website. NOT
Instruction set reference
Don't know why you need me to do your google searches for you.
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