# 8085 address question.....

#### RRITESH KAKKAR

Joined Jun 29, 2010
2,829
Alright, I have decoded A15 A14 A13 to single 8 bit addr by 74138 ( 3 to 8 decoders).
My PROM is of 8Kbytes and RAM is also same ( 2864 & 6264) the PROM is set at 0000H to 1FFFH by chip enable of Yo of 74138 chip and RAM at 4000H to 5FFFH from Y2 of 74138 chip to chip select of memory IC....

The problem is that,i don't understand why other pin of 74138 decoder are working, mean only Y0 and Y2 should give output as i am using only these addr 0000H to 1FFFH by chip enable of Yo of 74138 chip and RAM at 4000H to 5FFFH...

please clear my doubt, by putting some light of your experience...

#### t06afre

Joined May 11, 2009
5,934
The output from the 74xx138 is active low if I remember correct. Chip select is most often(99.99%) active low on processor auxiliary for cores like the 8085 and the Z80

#### RRITESH KAKKAR

Joined Jun 29, 2010
2,829
The output from the 74xx138 is active low if I remember correct. Chip select is most often(99.99%) active low on processor auxiliary for cores like the 8085 and the Z80
This is not answer of my question, here i am asking why the program counter is running on other addr bits as i am using only 0000H to 1FFFH by chip enable of Yo of 74138 chip and RAM at 4000H to 5FFFH...??

#### t06afre

Joined May 11, 2009
5,934
If you do anything wrong then laying out (or soldering up) the address or data busses error like this may occur. I spent/wasted one week many many years ago. Then I mirrored the address buss on a Z80. I was making on a vero-boad. The error was much like the one you describe. Erratic address and data busses

#### nigelwright7557

Joined May 10, 2008
532
The output from the 74xx138 is active low if I remember correct. Chip select is most often(99.99%) active low on processor auxiliary for cores like the 8085 and the Z80
I dont know about the 8085 but the Z80 outputs refresh addresses for DRAM all the time.

#### t06afre

Joined May 11, 2009
5,934
I dont know about the 8085 but the Z80 outputs refresh addresses for DRAM all the time.
yes that is correct for the Z80, but this is valid only for the lower 7 bits of the adress buss. The rest do not change.

#### Papabravo

Joined Feb 24, 2006
13,909
If there is supposed to be a valid address on the bus for every cycle you might expect that to be the case. If on the other hand the address bus assumes an arbitrary state when there is no fetching to do then it is quite possible that you may see other addresses. What you won't see is valid strobes for the data like RD* and WR*

#### t06afre

Joined May 11, 2009
5,934
Most assemblers from that period default the code to start at adress 0x100h if you do not use the org statement in your code. The reason is that the lower address range was used for the CPU ISR coding. For both Z80 and 8085 I think
Can you post your current assembler code

#### Papabravo

Joined Feb 24, 2006
13,909
Doesn't matter what the code is used for. The question was "if all the instruction fetches are in the 8K range from 0x0000 to 0x1FFF(Y0-low), and all the data fetches are from the 8K segment from 0x4000 to 0x5FFF (Y2-low), then why are the other outputs of the decoder going low".

The answer revolves around what the address bus is doing when it is neither fetching an instruction nor reading and writing data. In particular what are inputs A, B, and C of the decoder doing, and further what are the G1, G2A, and G2B enables doing?

PS -- I'm really trying to get the OP to answer his own question, but I'm not having much luck.

#### t06afre

Joined May 11, 2009
5,934
PS -- I'm really trying to get the OP to answer his own question, but I'm not having much luck.
Yes the person closest to find the error is the OP him self. Perhaps a microcontroller project would be better for him. Since a microcontroller after all is in principle a pre wired microprocessor system on chip. I think perhaps the OP should leave this project for now. And take it up again then he has become more experienced. Such a project is not for beginners.

#### RRITESH KAKKAR

Joined Jun 29, 2010
2,829
And take it up again then he has become more experienced. Such a project is not for beginners.
Thanks for saying this....
Now i think 8085 is cool project

#### RRITESH KAKKAR

Joined Jun 29, 2010
2,829
The answer revolves around what the address bus is doing when it is neither fetching an instruction nor reading and writing data. In particular what are inputs A, B, and C of the decoder doing, and further what are the G1, G2A, and G2B enables doing?
OK, I am using G1 connected to GND and G2A and G2B to Vcc.. as per data-sheet..
The ABC pin of 74138 is connected to A15 to C A14 to B and A13 to A

#### RRITESH KAKKAR

Joined Jun 29, 2010
2,829
Code of 8085 for output at SOD ............

Rich (BB code):
;Flash a LED on SOD
;Top of RAM @ 0x4000

START:  LXI H, 4000h
SPHL

FLASH:  MVI A, 0C0h
SIM
CALL DELAY
MVI A, 40h
SIM
CALL DELAY
JMP FLASH

DELAY:  MVI A, 0FFh
MOV B, A
PT1:    DCR A
PT2:    DCR B
JNZ PT2
CPI 00h
JNZ PT1
RET

#### Papabravo

Joined Feb 24, 2006
13,909
OK, I am using G1 connected to GND and G2A and G2B to Vcc.. as per data-sheet..
The ABC pin of 74138 is connected to A15 to C A14 to B and A13 to A
I think you have this backwards.
G1 is an active high enable -- tie it to VCC
G2A and G2B are active low enables -- tie them to GND

#### Papabravo

Joined Feb 24, 2006
13,909
Code of 8085 for output at SOD ............

Rich (BB code):
;Flash a LED on SOD
;Top of RAM @ 0x4000

START:  LXI H, 4000h
SPHL

FLASH:  MVI A, 0C0h
SIM
CALL DELAY
MVI A, 40h
SIM
CALL DELAY
JMP FLASH

DELAY:  MVI A, 0FFh
MOV B, A
PT1:    DCR A
PT2:    DCR B
JNZ PT2
CPI 00h
JNZ PT1
RET
0x4000 is a really crappy place to put your stack pointer. When you call delay it will try to push the return address to 0x3FFF and 0x3FFE. The DELAY routine will execute up to the return instruction then it will try to return to the address at 0x3FFF and 0x3FFE. Problem is that since there is no memory there the PC will be loaded with garbage and off you go into the weeds.

The stack pointer (SP) should be initialized to 0x5FFF for absolute safety. Sure this will waste a byte since the SP is decremented before any data is stored. After you get things working you can experiment.

#### stahta01

Joined Jun 9, 2011
133
FYI:

The IO/M* pin (likely pin 34) likely needs hooked up to the 74138; when that pin is low then the 8085 is accessing memory. When high it is doing a non regular memory operation.
It is doing IO operation instead.

Tim S.

#### tgotwalt1158

Joined Feb 28, 2011
110
Alright, I have decoded A15 A14 A13 to single 8 bit addr by 74138 ( 3 to 8 decoders).
My PROM is of 8Kbytes and RAM is also same ( 2864 & 6264) the PROM is set at 0000H to 1FFFH by chip enable of Yo of 74138 chip and RAM at 4000H to 5FFFH from Y2 of 74138 chip to chip select of memory IC....

The problem is that,i don't understand why other pin of 74138 decoder are working, mean only Y0 and Y2 should give output as i am using only these addr 0000H to 1FFFH by chip enable of Yo of 74138 chip and RAM at 4000H to 5FFFH...

please clear my doubt, by putting some light of your experience...
I think your address selection range is not correct. For Yo, should be F0000~F1FFF and for Y2, should be F4000~F5FFF. If it does not work, then
there may be some coupling going on at enable and input select. Another way is to use 74139 instead of 74138 and cascade the outputs.

#### t06afre

Joined May 11, 2009
5,934
The reset vector for the 8085 is 0x0000h So putting the ROM in the lower part is correct. I also think the I/M* pin of the 8085 is not needed if the system use memory mapped IO with decoding. This may simplify the design somewhat. I think this thread is going nowhere as the OP has not provided any schematics for the current setup. As he has put the design on a vero-board some schematics have to exist.

#### RRITESH KAKKAR

Joined Jun 29, 2010
2,829
I think you have this backwards.
G1 is an active high enable -- tie it to VCC
G2A and G2B are active low enables -- tie them to GND __________________
Sorry, i wrote this in hurry...
the G..pin are connected right as per data sheet.