How do you implement a 4-input function using a 8 x 1 mux using two 4x1 muxes?
I build a truth table and an abridged table. I have no idea how I would connect it to a it in b2 logic. so if F(a,b,c,d) = E(1,5,6,9,10,13,15) and i solved it as a function of a. How would i connect it up using a 74153 mux?

B C D F
0 0 0 0
0 0 1 1
0 1 0 A
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 A'
1 1 1 A

 

I can't tell what your design constraints are, because the question, "How do you implement a 4-input function using a 8 x 1 mux using two 4x1 muxes?" makes little since. What is using an 8x1 mux and what is using two 4x1 muxes?

 

Sorry. I'm not using a 8 to 1 mux at all. I'm implementing that function above using a two 4 to 1 mux which is a 74153. So i know that a 74153 mux can be use as a 8 to 1 mux. But how?

Here's what I tried doing. However I don't think this is correct.

 

It still isn't clear what you are trying to do. Are you trying to implement an 8:1 mux using two 4:1 muxes, or are you trying to implement a function of four variables using an 8:1 mux?

In your diagram, you have seven inputs (G, A, B, and then C0 through C3). How do these map to the four inputs (a, b, c, d) in your original problem description?

What are the constraints in your problem? Can you ONLY use two 4:1 muxes? In your diagram you are also using an OR gate. You didn't say anything about being able to use other gates in your problem statement. What other gates can you use (or not use)?

 

I figured it out already. I'm trying implement an 8:1 mux using two 4:1 muxes. So that is why a OR gate was needed. What wasn't clear to me at first was I have to use ground for 0 and vcc for 1.
My input would just be ABCD.

 

Are you sure about that?

By "my input would just be ABCD", what do you mean? Where do each of these go? Keep in mind that the channel select pins of the two muxes are shared in the part you are using?

 

Are you sure about that?

By "my input would just be ABCD", what do you mean? Where do each of these go? Keep in mind that the channel select pins of the two muxes are shared in the part you are using?

I think the OP means that he/she is implementing the function in the first post using a 74153 configured as a 8-to-1 mux....

 

That is what I think, as well. But configuring it as an 8:1 mux by just ORing the output of the two 4:1 muxes requires exploiting a feature of the chip that a generic 4:1 mux wouldn't (or at least might not) have. Even after you configure it as an 8:1 mux, implementing a 4-input function, while straightforward, requires some thought.

To implement an arbitrary function of four variables, you need an OR and two inverters in addition to the '153. You can get all of these from a single quad-NOR package.

 

Using the 74153, one could implement this design using nothing but two inverters and an OR...


With the function described in post 1, you could use b and b' for each of the strobe lines... this will guarantee the output is low... when ORed with the other 4-to-1 mux output, this will result in the output being reflective of the other mux.....

Are you allowed to use other gates?

Edit: looks like WBahn beat me to it....

 

Using the 74153, one could implement this design using nothing but two inverters and an OR...


With the function described in post 1, you could use b and b' for each of the strobe lines... this will guarantee the output is low... when ORed with the other 4-to-1 mux output, this will result in the output being reflective of the other mux.....

Are you allowed to use other gates?

Edit: looks like WBahn beat me to it....

OR and Inverters. I finished the implementation already. I used an inverter on b, so b is connected to the 1st strobe and b' is connected to the 2nd strobe. A is connected to 1-C2 an A' is connected 2-C3. Input D is connected to A on the 153 and input C to B on the 153. VCC or 1 is connected to 1-C1 and 2-C3 and the rest is connected to ground or 0.