8-Bit Shift Register in Verilog

Discussion in 'Homework Help' started by Carrosion, Oct 16, 2011.

  1. Carrosion

    Thread Starter New Member

    Oct 16, 2011
    I have to make an 8-Bit shift register that has reset, load, hold, shift left and right in verilog at gate-level/structural, I have made a 4-bit version of it using logicworks and help from some schematics I found; http://imageshack.us/f/513/4bitshifter.jpg/ and right now I am having some trouble making it in verilog, what I have so far is this:

    Code ( (Unknown Language)):
    2. module strucSh(LSR_out, dl, data_in, dr, L, D,  reset, clock
    3.     );
    4.      parameter regwidth = 8;
    5.      output [7:0] LSR_out;
    6.      input dl;
    7.      input [7:0] data_in;
    8.      input dr;
    9.      input L, D, reset, clock;
    10.      reg[7:0] LSR;
    11.      mux  m0(LSR_out[0], LSR_out[1], data_in[0], dr, L, D,  reset, clock);
    12.      mux  m1(LSR_out[1], LSR_out[2], data_in[1], LSR_out[0], L, D,  reset, clock);
    13.      mux  m2(LSR_out[2], LSR_out[3], data_in[2], LSR_out[1], L, D,  reset, clock);
    14.      mux  m3(LSR_out[3], LSR_out[4], data_in[3], LSR_out[2], L, D,  reset, clock);
    15.      mux  m4(LSR_out[4], LSR_out[5], data_in[4], LSR_out[3], L, D,  reset, clock);
    16.      mux  m5(LSR_out[5], LSR_out[6], data_in[5], LSR_out[4], L, D,  reset, clock);
    17.      mux  m6(LSR_out[6], LSR_out[7], data_in[6], LSR_out[5], L, D,  reset, clock);
    18.      mux  m7(LSR_out[7], dl, data_in[7], LSR_out[6], L, D,  reset, clock);
    19. endmodule
    Code ( (Unknown Language)):
    1. module mux(LSR_out, dl, data_in, dr, L, D,  reset, clock
    2.         );
    3.         output LSR_out;
    4.         input dl, data_in, dr;
    5.         input L, D;
    6.         input    reset, clock;
    7.         wire LSR_out, dl, data_in, dr, L, D, reset, clock;
    8.         wire rOut, lOut, loadOut, orOut, holdOut;
    11.         and(rOut, dr, ~L, ~D);
    12.         and(lOut, dl, L, ~D);
    13.         and(loadOut, ~L, D, data_in);
    14.         and(holdOut, ~L, ~D, LSR_out);
    15.         or(orOut, rOut, lOut, loadOut, holdOut);
    17.         flipflop fl(clock, orOut, reset, LSR_out);
    18. endmodule
    Code ( (Unknown Language)):
    1. module flipflop(clk, d, reset, LSR_out);  //Port List
    2.     input clk, d, reset;
    3.     output LSR_out;
    4.     wire x, y, q, q_bar;
    5.     wire d, clk, reset, LSR_out;
    7.     nand (x, d, clk);
    8.     nand (y, ~d, clk);
    9.     nand (q, x, q_bar);
    10.     nand (q_bar, y, q);
    12.     and (LSR_out, q, reset);
    14. endmodule
    Is this how I would represent it in verilog or is there something wrong in it?

    I do not have a tester for it either because honestly, I don't really know how to write tests yet[​IMG][​IMG]