8-Bit Shift Register in Verilog

Thread Starter


Joined Oct 16, 2011
I have to make an 8-Bit shift register that has reset, load, hold, shift left and right in verilog at gate-level/structural, I have made a 4-bit version of it using logicworks and help from some schematics I found; http://imageshack.us/f/513/4bitshifter.jpg/ and right now I am having some trouble making it in verilog, what I have so far is this:

Rich (BB code):
module strucSh(LSR_out, dl, data_in, dr, L, D,  reset, clock
     parameter regwidth = 8;
     output [7:0] LSR_out;
     input dl;
     input [7:0] data_in;
     input dr;
     input L, D, reset, clock;
     reg[7:0] LSR;
     mux  m0(LSR_out[0], LSR_out[1], data_in[0], dr, L, D,  reset, clock);
     mux  m1(LSR_out[1], LSR_out[2], data_in[1], LSR_out[0], L, D,  reset, clock);
     mux  m2(LSR_out[2], LSR_out[3], data_in[2], LSR_out[1], L, D,  reset, clock);
     mux  m3(LSR_out[3], LSR_out[4], data_in[3], LSR_out[2], L, D,  reset, clock);
     mux  m4(LSR_out[4], LSR_out[5], data_in[4], LSR_out[3], L, D,  reset, clock);
     mux  m5(LSR_out[5], LSR_out[6], data_in[5], LSR_out[4], L, D,  reset, clock);
     mux  m6(LSR_out[6], LSR_out[7], data_in[6], LSR_out[5], L, D,  reset, clock);
     mux  m7(LSR_out[7], dl, data_in[7], LSR_out[6], L, D,  reset, clock);
Rich (BB code):
module mux(LSR_out, dl, data_in, dr, L, D,  reset, clock
        output LSR_out;
        input dl, data_in, dr;
        input L, D;
        input    reset, clock;
        wire LSR_out, dl, data_in, dr, L, D, reset, clock;
        wire rOut, lOut, loadOut, orOut, holdOut;
        and(rOut, dr, ~L, ~D);
        and(lOut, dl, L, ~D);
        and(loadOut, ~L, D, data_in);
        and(holdOut, ~L, ~D, LSR_out);
        or(orOut, rOut, lOut, loadOut, holdOut);
        flipflop fl(clock, orOut, reset, LSR_out);
Rich (BB code):
module flipflop(clk, d, reset, LSR_out);  //Port List
    input clk, d, reset;
    output LSR_out;
    wire x, y, q, q_bar;
    wire d, clk, reset, LSR_out;

    nand (x, d, clk);
    nand (y, ~d, clk);
    nand (q, x, q_bar);
    nand (q_bar, y, q);
    and (LSR_out, q, reset);

Is this how I would represent it in verilog or is there something wrong in it?

I do not have a tester for it either because honestly, I don't really know how to write tests yet