I have another question I am stuck on, any help would be much appreciated!

Design a 8-to-1 line multiplexer using:
1. a 3-to-8 line decoder, 8 2-AND gates and 1 OR gate.
2. Two 4-to-1 line multiplexers and one 2-to-1 line multiplexer.

 

You should be able to figure out how to do it with the parts listed in (2) pretty readily.

For the parts listed in (1), I'm assuming that the OR gate has an arbitray number of inputs. So here is what should be a pretty big hint - you need an 8-input OR gate.

 

Thanks again for the help, I think I got it.

Just for part 2, I'm not sure how the truth table should look.

For a 3-8 multiplexer,there should be only 3 inputs correct?

But when I take two 4-1 mux and one 2-1 mux, there is 5 inputs all together.. am I doing that right?

 

I don't know what you mean by a 3-to-8 multiplexer. You have a 3-to-8 decoder - a very different thing. What you are trying to create is an 8-to-1 multiplexer, which is going to have 11 inputs, normally 8 data inputs and 3 channel select inputs, and one output.

 

Design a 8-to-1 line multiplexer using:
1. a 3-to-8 line decoder, 8 2-AND gates and 1 OR gate.

The meaning of 1. just like this:
You can connect the other lines.
D1 is the input Data.

 

Assuming this is correct, is the OP supposed to submit this as their answer, along with the Drawn by Scott Wang notation? That would only seem fair, that you get the credit for doing the OP's work for them, doesn't it? Or were you intending for the OP to submit your work as their own?

There's a reason why the guidelines for this forum strongly discourage simply providing answers and, instead, guiding the posters toward the solution.

But that is assuming that you solution was correct. It doesn't even seem to make sense, to me. You have a single data input, D1, and a single data output, the output of the OR gate. Regardless of what the state of the address inputs, A[2:0], the data input will appear at the data output provided the chip output is enabled. Well, we can get rid off everything except one AND gate if that's all we want to accomplish!

An 8:1 multiplixer has 8 data inputs. There are then three select lines to choose which of those 8 data inputs is fed to the single data output.

 

I drew it out a different way that I think is right.. but thanks for the help.. you guys are awesome!

 

Show us how you drew it out and we will be happy to either confirm that you got it or point out where it has problems.

 

Assuming this is correct, is the OP supposed to submit this as their answer, along with the Drawn by Scott Wang notation? That would only seem fair, that you get the credit for doing the OP's work for them, doesn't it? Or were you intending for the OP to submit your work as their own?

There's a reason why the guidelines for this forum strongly discourage simply providing answers and, instead, guiding the posters toward the solution
...
...
An 8:1 multiplixer has 8 data inputs. There are then three select lines to choose which of those 8 data inputs is fed to the single data output.

Thanks.
Bertus already showed me the rules.

If you disconnect the common point of 8 AND gates, and then the 8 input of AND gates will become the 8 data input D0~D7.

If you change 2 input AND to 3 input AND gates, then you will get the ENA for the AND gates.