74LS90 chip

Thread Starter

nismospecv

Joined Mar 14, 2007
10
Does anybody have any information on how to make a divide-by-2 counter and a divide-by-4 counter using 7490 chips?

I'm not really sure how to even go about making a table for this to get me started.

If you already know the pin layout for creating it, that would be helpful also.
 

Thread Starter

nismospecv

Joined Mar 14, 2007
10
This doesn't make sense to me. What do you mean by use pin 12 for divided by 2?

Also, what would a divide-by-3 look like?
 

thingmaker3

Joined May 16, 2005
5,084
The signal on pin 12 will be 1/2 the frequency of the signal on pin 14.

Look at one of the datasheets in the link I provided.

Divide-by-three will require more than just a 7490. You'll have to reset the chip every third clock cycle with external logic.
 

Salgat

Joined Dec 23, 2006
221
Couldn't you do an approximate divide-by-3 by tying QA and QB to the ANDing MR0? That way when it hits 3 it resets to 0 and then has to count 3 times again to get back to 0(a pulse every 3 pulses for QB)?
 

thingmaker3

Joined May 16, 2005
5,084
I think that would work! It should be quite precise at lower frequencies, too - only a few dozen nanoseconds too long of a pulse at pin 9. Similarly, one could get approximate divide-by-five or divide-by-nine from using pin 8 or pin 11, respectively.

One could also divide-by-seven by ANDing pins 12 and 8 in bi-quinary mode.

Congratulations, Salgat! Its a divide-by-n counter!
 

Iommi

Joined Jun 3, 2007
1
I apologize, but I don't understand Salgat's answer to the "divide by 3" question. What exactly must I do in order to use 7490 IC's in a divide by 3 configuration. Thank you so much for your patience.
 

Salgat

Joined Dec 23, 2006
221
Tie the pins QA(Q1) and QB(Q2) to the pins MR0, which has 2 inputs. By tying each output to the different MR0 inputs, the counter will reset when the counter reaches 3. A schematic might be needed if you don't understand :\
 
Top