6-to-64 Decoder with Smaller Decoders

Discussion in 'Homework Help' started by tquiva, Oct 22, 2010.

Oct 19, 2010
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This is what's stated in the problem:
Show how to implement a 6:64 decoder using smaller decoder parts. Implement your design in LogicWorks using the decoder parts in the 7400.clf library. Make sure your file is ready to simulate to show your decoder works properly. Think of creative ways to display your outputs to be understandable, and be sure to document them for the grader, explaining what (s)he should see. Arrange your circuit so that it fits on one printed page, and so that it is easy for the grader to change inputs and see the results in one screen.

So I did this by cascading smaller decoders. I used 1 2-to-4 decoder and 4 4-to-16 decoders. I used the 2-to-4 as an enable decoder for all the other decoders. I am trying to display the outputs of my 6:64 decoder. The device I used for the 4:16 is a 74154 with active low outputs and enable inputs. So therefore, do I use AND gates to display the maxterms? Do I connect them to binary probes?

Because one thing I noticed is that for each output, it only contains one maxterm. So how would I use an AND gate with two inputs? Do I ground the other input?

Are all my outputs suppose to be 0 or 1? I think it's suppose to be 0 but I just want to make sure.

Could someone experienced with LogicWorks please help me out. I've been frustrated with this for hours. Any help will be greatly appreciated.

Last edited: Nov 27, 2010
2. Georacer Moderator

Nov 25, 2009
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Every output pin corresponds to one maxterm. You don't neet anymore gates to detect it, the decoder does that for you.

The active output is the 0, not the 1, so the schematic is correct from this aspect too. Notice the dot in the base of the ouput pin. This means that the activated pin (pin 10 for example) will go LOW. HIGH is the OFF level.

Oct 19, 2010
176
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Thank you so much for the feedback. Will I need to make any corrections to the schematic? Did I label all the signals correctly? (eg. 15=31=47=63=M15)

4. Georacer Moderator

Nov 25, 2009
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In the 74139 you correctly put the MSB on pin 2 and the next digit on 3. But on the 74154 the MSB is D not A. Just invert the order of the inputs.

You also forgot a NOT for the last 74154 Enable pins.

Oct 19, 2010
176
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Like this?

Last edited: Nov 27, 2010
6. Georacer Moderator

Nov 25, 2009
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1,289
Correction of previous statement: I told you to add the missing NOT gate for the last 74154 IC, but on second thought, you don't need the NOT gates at all. The 2-to-4 Decoder has an active LOW output, and the enable of the 74154 is LOW too. So putting NOT gates between them is actually a mistake. Delete the NOT gates for correct circuit performance.

The pin layout seems correct.

Oct 19, 2010
176
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But if I have inputs a & b constantly set to 0 on the switch, wouldn't I need those three inverters at the last three outputs?

8. Georacer Moderator

Nov 25, 2009
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I was talking about the NOT gates, connecting the outputs of the 74139 with the Enable inputs of the 74154s. I said these NOT gates must be removed.

I said nothing about inputs a and b.

Oct 19, 2010
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I'm sorry. I'm still very new to this. Are you talking about removing the bubbles from the outputs of the 74139? Because I'm not sure if I am able to do that?

10. Georacer Moderator

Nov 25, 2009
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Remove these:

How do you call them?

Apr 5, 2008
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Hello,

@Georacer:
The gates you are pointing at are NOT gates, also called inverters.
See the datasheet of a 7404 (TTL) or the 4049 (CMOS).

Bertus

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• sn5404.pdf
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Oct 19, 2010
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Hi Bertus. Do you think I should remove the inverters? Or is my logic diagram ok?

13. Georacer Moderator

Nov 25, 2009
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I think I wouldn't be able to write a 2-post long essay on FSM implementation without knowing what a NOT gate is or looks like.

The question was for the OP who wouldn't recognise it by name. After pointing the gate I asked him if he knew it by some other name.