Hi, right now I have a signal that is either high(5V) or low(0V). Is there any circuit that can make this signal when it is high, it's 5V and when it is low, it is -5V instead of 0V? I have tried to use a summing amplifier to subtract the signal by 5V, when it is low. And when it is high, I dont subtract the voltage by 5V. However, the circuit doesnt work in simulation. Please see the attached file for the circuit A is the signal that is 5V, when high and 0V when low. S1 and S4 are on when the signal A is high. S2 and S3 are off when the signal A is low. S1 and S4 are on when the signal A is low. S2 and S3 are on when the signal A is high. The op-amp will produce -5V when R1 and R2 are equal. When the signal A is low, Vout = -((R1/R2) * 5 + (R1/R3) *A) Since A is 0V, Vout = -5V. Where did I make mistake in this circuit? Btw the output is connected to an inverter.
A much simpler way is to use two pseudo-inverters referenced to -5V instead of ground. These can be either BJT or FET based. For BJT select appropriate base resistor to limit the base current or for FET make sure that the Vgs max is larger than 10V.
Thank you for the reply. I still have some questions, though. First of all, according to Spectre if Vgs is larger than 10V then it exceeds the oxide breakdown voltage. Secondly, I think the output swing is limited to the 5v and (-Vtn)...not sure if that is right though.
Thank you for the reply. I still have some questions, though. First of all, according to Spectre if Vgs is larger than 10V then it exceeds the oxide breakdown voltage. Secondly, I think the output swing is limited to the 5v and (-Vtn)...not sure if that is right though.
Thank you for the reply. Yeah that is a good idea...but I would like to minimize the area of the chip...
The first transistor should be an PMOS instead of NMOS. If your process can not handle Vgs > 10V then you have to use double-level which is quite complicated. Why do you bias the bulks with clocked voltages? Output swing is limited by the bulk biases (process related) and the output driver topology (circuit design). Of course you could use a comparator, but if I gather correctly that this is a chip level design, then you have to design the comparator to swing to +/-5V. You would eventually hit the same problem.
Well you can get 8 pin dip ICs that will do it. Another way that is a little larger and a little out of the norm is a MAX232. A few 1uF caps around it and you can feed the TTL (0V to 5V) signal in and you get an RS232 signal out (+5V to _5V). You only need a +5V supply as the chip makes its own -5V. Only problem is I believe the O/P would be inverted.
Thank you for the reply. I changed the first transistor and R1 and the circuit is working very well. The clocked voltages that are biased to the bulks were actually acting like dc voltages. Anyway, I changed them to vdc instead of vpulse.
