555 oscillator stability? (ans'd)

Thread Starter

metermannd

Joined Oct 25, 2020
216
How stable is the 555 as an oscillator?

What I'm looking at is something that will give me a 5V / 12.5kHz square wave (as in 50% duty cycle).

I'm looking at having to redo my project from the bottom up, and one of the things that will likely have to go away is the MC6840 timer IC. Two of its channels are strictly software timers (which I could just as well recreate in code), the only one with a physical output is a 'set and forget' deal which generates a square wave, and I think a 555 should do just fine (my other option would be a Schmitt trigger oscillator).
 

crutschow

Joined Mar 14, 2008
27,907
I would expect it to be stable within a few percent with voltage and temperature if 1% resistors and a low temp-coefficient film or NPO ceramic (no electrolytics or standard ceramics) timing capacitor is used.

What stability do you need?
 

Papabravo

Joined Feb 24, 2006
16,961
How stable is the 555 as an oscillator?

What I'm looking at is something that will give me a 5V / 12.5kHz square wave (as in 50% duty cycle).

I'm looking at having to redo my project from the bottom up, and one of the things that will likely have to go away is the MC6840 timer IC. Two of its channels are strictly software timers (which I could just as well recreate in code), the only one with a physical output is a 'set and forget' deal which generates a square wave, and I think a 555 should do just fine (my other option would be a Schmitt trigger oscillator).
You may have some trouble getting exactly a 50% duty cycle. How close to 50% does it need to be? If you want accurate and stable and a 50% duty cycle then a crystal oscillator is what you need. To be fair you have not specified what accuracy and stability you require, so it is hard to advise you correctly.
 

sparky 1

Joined Nov 3, 2018
587
The 29 pin programmable timer 4 MHz, 3 asynchronous external timers with interrupts ect.
The data and clock waveforms if not syncronized might produce errors over time, possible problems using 555 depending on the application.
I do see how inserting a one shot might improve a faulty timer, the stability is temperature coefficient of RC and supply variation both I and V.
http://pdf.datasheetcatalog.com/datasheet/motorola/MC6840.pdf

A new microcontroller module would be capable of most any timing needs and would supercede capability and possibly operation.
the cost is low enough thinking about your time spent on the later technology rather than splice mod.
 
Last edited:

Deleted member 115935

Joined Dec 31, 1969
0
How stable is the 555 as an oscillator?

What I'm looking at is something that will give me a 5V / 12.5kHz square wave (as in 50% duty cycle).

I'm looking at having to redo my project from the bottom up, and one of the things that will likely have to go away is the MC6840 timer IC. Two of its channels are strictly software timers (which I could just as well recreate in code), the only one with a physical output is a 'set and forget' deal which generates a square wave, and I think a 555 should do just fine (my other option would be a Schmitt trigger oscillator).
What accuracy do you need ,
both in terms of PPM over what temperature , how accurate / stable is the power voltage
an din terms of the mark space ratio,

The 555 is generally "terrible" compared to a real clock source, but might be sufficient for what you want .
 

AnalogKid

Joined Aug 1, 2013
9,385
If you need crystal accuracy and stability for the 12.5 kHz clock source, consider the CD4060 with a 1.6 MHz or 3.2 MHz crystal. Or a 1.6 MHz integrated oscillator and any 7-bit (or more) binary counter such as a CD4024.

ak
 

Thread Starter

metermannd

Joined Oct 25, 2020
216
I guess the 555 is out. My concern was the possibility of drifting tens of Hz above or below, as this carrier gets fed into an XOR gate along with a bit stream, and which also is why I wanted a 50% duty cycle.

It occurred to me that one, a crystal oscillator is the better option, two, I ALREADY have a 1MHz crystal-based master clock, and three, this 12.5kHz carrier REALLY ought to be in sync with that clock.

Therefore, what I think I actually need instead is a divide by 80 counter. I could make one by cascading two 4018s, right? One set for divide by 10, and the other as divide by 8?
 

Papabravo

Joined Feb 24, 2006
16,961
I guess the 555 is out. My concern was the possibility of drifting tens of Hz above or below, as this carrier gets fed into an XOR gate along with a bit stream, and which also is why I wanted a 50% duty cycle.

It occurred to me that one, a crystal oscillator is the better option, two, I ALREADY have a 1MHz crystal-based master clock, and three, this 12.5kHz carrier REALLY ought to be in sync with that clock.

Therefore, what I think I actually need instead is a divide by 80 counter. I could make one by cascading two 4018s, right? One set for divide by 10, and the other as divide by 8?
As long as you are looking at a 2-chip solution I would try a fixed divide by 10 and a divide by 8, a 4160 and a 4161. OTOH using two available parts has a certain attraction. Either way should be just fine.
 

AnalogKid

Joined Aug 1, 2013
9,385
Two pieces of any 4-bit presettable counter, BCD or binary, can be strapped to produce a symmetrical divide-by-80. If you have a spare gate or two in the area, then any single-chip, dual 4-bit counter (again, BCD or binary) can be gated to produce the same. If you don't have a gate handy, a diode-OR will work.

ak
 

Deleted member 115935

Joined Dec 31, 1969
0
If you use the output of the counter as the clock,
this is asynchronous to the clock that is clocking the counter,
depending upon the counter, this might be close , might not,

Ideal for a cpld this,
The way to get a good clock, is to re register the output of the counter to the same clock as the counter works on,

Now with a CPLD, you could do the clock generation,
and the XOR you want,

Is the idea to manchester encode the data stream so that you have clock info in the data stream ?
 

AnalogKid

Joined Aug 1, 2013
9,385
My guess is that perfect phase alignment is not necessary, but a constant phase relationship is. The phase delay through 7 counter stages should be less than 50 ns, and could be down in the 30's. That's 3% at 1 MHz, AND 0.04% AT 12.5 kHz.

AK
 

Thread Starter

metermannd

Joined Oct 25, 2020
216
I guess I learned something new today - I'd always wondered why the 12.5kHz clock was XOR'd with the output from the PIA chip... yes, this setup does use Manchester encoding.

I am looking at Arduino or a FPGA at this point and have begun dissecting the 8K of assembly to see how best to rewrite it in some flavor of C.
 
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