In 555 timer astable circuit with constant current source, capacitor is fully discharging and giving 0-2/3Vcc instead of 1/3Vcc -2/3Vcc.What could be the possible reason?

 

Because the discharge pin (which is an open collector pulldown) is directly connected to the cap.

When discharge switches on you get a very high current discharge pulse that will fully discharge the cap. It also risks damaging the 555 timer.

You need to add a resistor in series with pin 7, so the discharge takes some time, and gives time for the internal comparator to sense the cap voltage is under 0.3Vcc and end the discharge cycle.

 

Thanks,I was also suspecting the same reason,but was not sure.
During design, it gives perfectly fine result in simulations.
I avoided resistor because I wanted to have a perfect saw tooth voltage waveform,as it gives slightly sloppy discharging. anyway, what minimum value of resistor would do to not have sloppy discharge but 1.7 V pk-pk ?

And I need one more opinion of yours regarding this circuit, its frequency appears to be somewhat unstable.i.e,it changes as we add more components on the PCB board, and in the first place the frequency theoretically calculated and that simulated do match but not on actual circuit, Is it bias point unsuitability that lets charging current to vary in case of different components attached?
How to cater for this effect?

 

555 timers are not the most accurate of ICs for timing. If you want to boil an egg or have a kitchen timer up to say 20 minutes then it will be fairly accurate, but long time periods and precision accuracy is unlikely. Adding components etc. will indeed change the characteristics of the circuit and hence the output frequency.

With regard to it not simulating the same as in the real world, more often than not simulations work with what they term "ideal" components, which means that no external factors such as temperature etc. are taken into account. This means that the circuit most probably will behave/time slightly differently in the real world. In some instances circuits may not simulate but may work fine in real life, for example, I am building a clock circuit and I get "convergence" errors because Multisim is unable to simulate it... but in real life it works fine.

 

Given that 555 Timers are not the best choice for precision and accuracy, still I've seen many sophisticated circuits using 555 Timers,

and even if not suitable for accurate use but I want to know the reason of this behavior , why adding components on discharge pin side and on pcb, changes its frequency which factors would possibly be playing role here?

 

Thanks,I was also suspecting the same reason,but was not sure.
During design, it gives perfectly fine result in simulations.
I avoided resistor because I wanted to have a perfect saw tooth voltage waveform,as it gives slightly sloppy discharging. anyway, what minimum value of resistor would do to not have sloppy discharge but 1.7 V pk-pk ?
...

I can't say for sure. Try a 10 ohm or 22 ohm, if that is not enough then just increase it until the bottom trigger voltage seems right. Keep in mind even a 99:1 duty cycle for a sawtooth generator is considered good. Using just a crude 555 you may have to settle for slightly worse than that.

A CMOS 555 like a 7555 will have much faster and cleaner switching, and will improve your circuit.

As for the freq accuracy, 555 timers are terrible and you will be lucky to get the freq stable to within 1 or 2% generally.

Caps will drift in value as they heat from operation, and anything you add to the breadboard or PCB will affect your stray capacitances and affect frequency too.

What you REALLY need to do is state what you need the sawtooth generator for, and what it will be driving, and actual specs like what frequency, duty cycle etc you need for your final application. Then we can suggest the best way of doing the whole job instead of just debugging general 555 issues in a circuit that will never work well.

 

Another reason why your calculation and your sims might not match reality is that they might not be taking into account the Early effect i your current source. The simulation might be, if you've got a model for the specific transistor part number you are using. The Early effect simply says that the collector current in a transistor will increase with increasing collector-emitter voltage even if the base current is held fixed. The result is that at lower voltages on the capacitor you will get higher charging current than at higher capacitor voltages.

 

Because the discharge pin (which is an open collector pulldown) is directly connected to the cap.

When discharge switches on you get a very high current discharge pulse that will fully discharge the cap. It also risks damaging the 555 timer.

You need to add a resistor in series with pin 7, so the discharge takes some time, and gives time for the internal comparator to sense the cap voltage is under 0.3Vcc and end the discharge cycle.

I don't buy that. The typical monostable application circuit in the datasheet doesn't have a current limiting resistor.
Have you experienced this problem?

EDIT: Maybe with a LARGE capacitor...

 

Big cap., small cap, makes no difference. The discharge current is limited by the effrective series resistance of the discharge transistor which is sized in order to match that resistance to the maximum current it can handle

 

Big cap., small cap, makes no difference. The discharge current is limited by the effrective series resistance of the discharge transistor which is sized in order to match that resistance to the maximum current it can handle

Yeah, but I was thinking of a BIG cap, like 1 Farad.
Let's say we hang a 1F cap on pin 7. The cap is charged to 10V, and the pin 7 current is beta-limited to 200mA. The cap discharges at dv/dt=I/C=200mV/sec. The power dissipation starts out at P=10V*200mA=2W, and decreases by 200mW/sec. The IC is going to get pretty hot, or die, before the power gets down to a tolerable level.

Yeah, I know, you would have to pay over $100 for such a cap. It would be a ridiculous way to use a 555. That's why my original statement was, that I didn't buy it. Then I figured that if I left a loophole, someone else would use it if I didn't.

 

Yeah point taken, I was probably extravagant with the claim that the 555 would be damaged not having a series resistor on the pin.

As for the cap voltage going too low (below 1/3 Vcc), I have seen similar things with no series resistor on pin7 especially when the \ slope is very fast and there may be external capacitances (from a breadboard etc). The internal comparator of the 555 is a bit slow to switch, and the discharge transistor on pin7 is a bit slow to turn off. You really need a bit of a delay there from a series resistor if you want a reliable 1/3 Vcc lower trigger point.

 

Yeah point taken, I was probably extravagant with the claim that the 555 would be damaged not having a series resistor on the pin.

As for the cap voltage going too low (below 1/3 Vcc), I have seen similar things with no series resistor on pin7 especially when the \ slope is very fast and there may be external capacitances (from a breadboard etc). The internal comparator of the 555 is a bit slow to switch, and the discharge transistor on pin7 is a bit slow to turn off. You really need a bit of a delay there from a series resistor if you want a reliable 1/3 Vcc lower trigger point.

Exactly. even with modest duty cycles, high frequency astables will run at lower than predicted frequencies, due to the delay of the Schmitt trigger and to stray and device capacitances.

 

I don't buy that. The typical monostable application circuit in the datasheet doesn't have a current limiting resistor.

if you know this, then Please suggest possible reason

 

I wonder also if this issue is related to the minimum trigger pulse width requirement of the particular 555 timer.

One might perhaps verify this by inserting a suitable resistance in series with the timing capacitor which can force the trigger input signal to transit the 1/3Vcc value in a more "defined" manner - i.e. in consideration of the interval set by the negative transition through 1/3Vcc and the subsequent positive transition through 1/3Vcc. This transition time may then represent the minimum trigger pulse requirement which might then account for the low value [less than 1/3 Vcc] observed [in the OP's case] at the point of common connection at the capacitor terminal.

 

You should add decoupling caps between V+ and Gnd (0.1uf ceramic and 10-47uf in parallel) and .01uf from pin 5 to Gnd.

The cap from pin 5 to Gnd is frequently ignored in 555 circuits but some
circuits/chip variants don't work properly (or at all) without it.
I made an IR repeater with a cmos variant 555 which would not work until I
added that cap.

Check this out:
[thread=45583]Bypass Caps[/thread]