4bit synchronous counter using D Flip Flops

Discussion in 'Homework Help' started by dankipiti, Feb 13, 2005.

  1. dankipiti

    Thread Starter New Member

    Feb 13, 2005
    This is an assignment for my Uni. I have to implement a synchronous counter using D Flip Flops. It should look something like this. http://babbage.cs.qc.edu/courses/cs343/200...signment_02.php

    I have on paper done all the combination logic and determened the inputs for all the flip flops.
    A0 = ~A0
    A1 = (~A1 A0) + (A1 ~A0)
    A2 = (~A1 A2) + (A2 A1 ~A0) + (~S2 S1 S0)
    A3 = (A2 A3) + (A3 ~A1) + (A3 ~A0) + (~A3 A2 A1 A0)

    The inputs to A0 and A1 were given but I dont understand the logic behind the inputs to the "AND" and "OR" gates. How to know which wire to assign as their inputs.For example, the ~Q output of A1 goes into an "AND" gate which leads back to the input of A1, why? Thanks in advance for any help.
  2. dragan733

    Senior Member

    Dec 12, 2004
    One constructs a table with inputs parameters Q0, Q1, Q2, Q3 and outputs parameters D0, D1, D2, D3. Then with minimization of this table with, carnaugh map, one gives:


    Then you have a mistake, at the first term of D3. You wrote Q2Q3. It needs to be: Q2'Q3