4 Variable 8:1 Multiplexer HW Help

Thread Starter


Joined Oct 4, 2011
Hi, I am new to this forum and am having difficulty understanding the concept of a 4 variable 8:1 multiplexer HW question. I am asking to confirm if I am on the right track or if my thinking is correct. I am not asking for someone to do my HW. Thanks in advance!

Basically the question gives a 4 variable function as:
F = ~C~D + ~B~C + ~ABC + ~A~D + ~B~D

It then ask to "generate F using a 8:1 multiplexer with control input B,C,D and minimal Nand Gates." This is the steps I have done so far.

I did a truth table with ABCD as inputs and for F output my minterms are:

For each of the groupings i then outputed as:
F = 1, A', A', 1,1,A',A',0

That is the part I am lost with. Basically the notes were a bit vague and I was confused. For an 8:1 multiplexer is this basically the right way to go? Or am I understanding this incorrectly. I notice in the notes that in the truth table they just drew the lines and used that to output the F function.

Here is a sketch of my final circuit drawing.

Also I do not understand the part on the question where it states: "...and minimal Nand Gates." Is that necessary? Or is my single inverter good enough? Thanks again. I just want to make sure I understand this correctly before I do the same method on a test.


Joined Dec 24, 2010
i did't understand what kind of simble(~) is
in dld..
please use correct function of F.
then i can give you suitable solution


Joined Sep 16, 2011
as I understand it ~ stands for NOT, so

\(F(ABCD) = \overline{C} \cdot \overline{D} + \overline{B} \cdot \overline{C} + \overline{A} \cdot B \cdot C + \overline{A} \cdot \overline{D} + \overline{B} \cdot \overline{D} \)

Anyhow, it seems to me that you used ABC as your Mux adress in your logical table (instead of BCD).

I got a solution with 1 NAND gate for inversion of A


Joined Nov 25, 2009
Maen is correct. You use the LSB for input to your MUX and the rest MSBs for addressing. That said, you need to connect A,B and C to the input select and D to the input of the MUX.

The NAND gate number might refer to the demand that you use only NAND gates to implement the circuit (instead of NOT gates).


Joined Sep 16, 2011
I put some more thoughts into this and maybe you have to use only A, B, C and D as entries (removing 1 and 0 as possible "entries"). this would add 2 NAND gates to the circuit : \(\overline{A \cdot \overline{A}}\) for 1 and an inverter after this for 0.

Even if this is theoretically correct it's something I would never use in practice since it's in my opinion quite unstable, prone to add some glitches on your logical signals and a wide open door for timing problems. But maybe the exercise asks for it.