I am very very new with VHDL,therefore there will be lots of newbie questions and posts.

I understood 2 to 1 mux,but not 4 to 1,

does this code make sense as im using a Cyclone II chip from Altera with 10 Switches and 4 Key Switches

This is my example given by altera

Instructions

1. Create a new Quartus II project for your circuit.
2. Create a Verilog module for the three-bit wide 5-to-1 multiplexer. Connect its select inputs to switches
SW17−15, and use the remaining 15 switches SW14−0 to provide the five 3-bit inputs U to Y . Connect the
SW switches to the red lights LEDR and connect the output M to the green lights LEDG2−0.
3. Include in your project the required pin assignments for the DE2 board. Compile the project.
4. Download the compiled circuit into the FPGA chip. Test the functionality of the three-bit wide 5-to-1
multiplexer by toggling the switches and observing the LEDs. Ensure that each of the inputs U to Y can be properly selected as the output M.

Does this code make sense?

entity chiong2 is
PORT( SW :IN STD_LOGIC_VECTOR (9 DOWNTO 0);
LEDR :OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
A,B,C:IN STD_LOGIC_VECTOR (2 DOWNTO 0));

end chiong2;

architecture Behavior of chiong2 is
begin
chiong2_1: process (A,B,C)
begin
case SW is
when "000" => LEDR <= A;
when "001" => LEDR <= B;
when "010" => LEDR <= C;

LEDR <= SW(1);
LEDR <= SW(2);
LEDR <= SW(3);

end case;
end process chiong2_1;

end Behavior;

 

Looks like you are missing two of the conditions for your mux (011 and 100). Also, you need to increase the bit widths of the multiplexer to satisfy the condition of the exercise. Finally, make sure to add two more mux inputs with bit widths equal to the output (4 downto 0).

Good Luck and let us know how it goes.