Hey everyone,
I need a little help with this problem. I am supposed to design and code (in pure structural verilog) a synchronous 4 bit counter that is triggered on positive clock edges and that resets back to 0 when the counter reaches 5. Any help in understanding this would be appreciated. Especially the what goes where, I am unclear on how the dff increments when there aren't any inputs, I'm assuming that the input is a pure logic 1. However, how does it recognize when I have reached 5 or any other number for that fact and know to enable the reset?
I need a little help with this problem. I am supposed to design and code (in pure structural verilog) a synchronous 4 bit counter that is triggered on positive clock edges and that resets back to 0 when the counter reaches 5. Any help in understanding this would be appreciated. Especially the what goes where, I am unclear on how the dff increments when there aren't any inputs, I'm assuming that the input is a pure logic 1. However, how does it recognize when I have reached 5 or any other number for that fact and know to enable the reset?
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