I have not yet begun this assignment because I do not know exactly how to start. I am going to create a state table for the counter, but I am confused on how to do this. I'm still a little new at this subject of counters and am wondering is someone is willing to help me get started?


The problem states:
Design a 4-bit Gray code counter that cycles through the sequence: 0000, 0001, 0011, 0010, 0110, 0111, 0101, 0100, 1100, 1101, 1111, 1110, 1010, 1011, 1001, 1000, and then back to 0000. (You can use an asynchronous Reset signal to reset the machine to its start state)

 

Do you understand the theory behind greycoding? (answer is in your sequence above, by example)

i.e. why does it exist?


Here is a link, either way, that shows how to convert between binary and GC, but a 4 bit counter wouldn't be that in-depth.

 

Yes. Two value differ in one bit.

What device would I use to implement this? Would I use flip flops or a 74163?

 

It is described in detail in This Patent Using D Flip Flops

Is this to be built using any logic IC availalbe, FPGA, or other?

What will the inputs be?

What format is the output expected to be in (LED, LCD, Logic Level, etc)

Post a schematic of what you have so far after reading the description in the link above.

 

I am to use any logic IC available. I'm not sure how to go about the inputs, but I will be using logic as output.

I am so lost and I am so unsure of how to begin this problem. How would you start it out?

 

Start with a 1Hz clock or similar input.

Play around in logisim (freeware java logic simulator) with flip flops until you get the lines out correctly. Mostly flip flops, but a few extra gates will be used as well.

 

Thank you very much. I almost got it.
But one more question.
How would I go about choosing what the inputs will be?

 

Just one input for counting, count the pulses from the 1Hz clock.

 

Alright, thanks. I'm a bit iffy about the way I went about doing this assignment but here's what I did.
I began by creating a state table for the counter, and then used the excitation table for a J-K FF to compute the J-K FF inputs of the counter. I then used the J-K inputs to create k-maps to derive the boolean equations. Lastly, I will then implement all my equations into a logic diagram.
Is my procedure correct?
Here's what I've done so far:

 

I didn't check every step of the gray code truth table nor every excitation column.

You didn't transfer the numbers from the state table to the Karnaugh map correctly. Pay more attention to the order of the bits Q3Q2Q1Q0. The function that you get depends on the correct placement of the numbers.

Don't forget to add a reset button for your FFs to drive them to the starting state.

 

What is the correct way to implement the state table into K-Maps?
For all the K-Maps, I used the present state variables, Q3 Q2 Q1 Q0. I Placed Q3Q2 on the top row and Q1Q0 on the left column. Based on these inputs, I placed the values for the J-K inputs.

Eg. Q3Q2Q1Q0 = 0000. J3 = 0
So I placed the 0 on the very top left box of the K-Map.

What did I do incorrectly?
And how would I go about adding a reset button to my FF?

 

The MSBs should go to the vertical side and describe the rows.
The LSBs should go to the horizontal side and describe the columns.

There isn't any predetermined way to position Q3, Q2, Q1 and Q0, the above is just a suggestion. It does make simpler though the way to fill the map from the state table data.

However, what must be valid at all times, is the relation between the minterms of the map and the state table. To show you your error, consider this.

In the state table, you positioned the 1 in the J3 column in the row Q3Q2Q1Q0=0100. But in the map you put the 1 in the place Q3Q2Q1Q0=0001. Do you see that this can't be right?

 

thank you so much. I realized that I labeled the variables incorrectly.
How do I add a reset button to my FF?
I'm planning to use a 7476 device, do you think this is the best device to use?

 

There's always the Microsoft reset, no bluescreen, just power it off and back on.

 

I tried implementing all of my boolean equations into LogicWorks 5.
My equations are:
J3 = Q2 * Q1' * Q0'
J2 = Q3' * Q1 * Q0'
J1 = (Q3' * Q2' * Q0) + (Q3 * Q1 * Q0)
J0 = (Q3' * Q2' * Q1') + (Q3' * Q2 * Q1) + (Q3 * Q2 * Q1') + (Q3 * Q2' * Q1)
K3 = Q2' * Q1' * Q0'
K2 = Q3 * Q1 * Q0'
K1 = Q3' * Q2 * Q0
K0 = (Q3' * Q2' * Q1) + (Q3' * Q2 * Q1') + (Q3 * Q2 * Q1) + (Q3 * Q2' * Q1')

The device I used is a 7476. I am so unsure if I implemented it correctly into this logic diagram. Are all my connections correct? And what are the PRE and CLR supposed to be?

 

When CLR=LOW and PRE=HIGH, FF is set to 0.
When CLR=HIGH and PRE=LOW, FF is set to 1.

Your schematics is faulty, propably because you didn't transfer the state table to Karnaugh maps correctly.

The correct input expressions are:
\(J3=Q2Q1Q0\\
K3=Q2Q1Q0\\
\\
J2=Q3'Q1Q0\\
K2=Q3Q1Q0\\
\\
J1=Q1'Q0\\
K1=Q1'Q0\\
\\
J0=Q1'\\
K0=Q1\\\)

I suggest you revise you Karnaugh map theory.