4 bit comparator vhdl problem

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY temp1 IS
        port(Ain,Bin : in std_logic_vector(4 downto 0);        
      PrevA,PrevB: in std_logic; 
      AgB, AlB: out std_logic);
END ENTITY temp1;

--
ARCHITECTURE structural OF temp1 IS
        signal s1,s2,s3,s4,s5,s6: std_logic;
component bit_slice_comp is
     port(A,B : in std_logic;        
      PrA,PrB: in std_logic;
      AgBout, AlBout: out std_logic);
    end component bit_slice_comp;

Begin
  comp_iterate: for i in 0 to 3 generate
  comp: bit_slice_comp port map (A=> Ain(i), B=> Bin(i), PrA => PrevA, PrB => PrevB, AgBout => AgB, AlBout =>AlB);
 --  comp: bit_slice_comp port map ( Ain(i)=>A,  Bin(i)=>B,  PrevA => PrA,  PrevB => PrB,  AgB => AgBout , AlB => AlBout );

      calculation: process
      begin
      s1<= Ain(i) and PrevA;
      s2<= Ain(i) and (not Bin(i));
      s3<= (not Bin(i)) and PrevA(i);
       
      s4<= PrevB(i) and Bin(i);
      s5<= Ain(i) and PrevB(i);
      s6<= (not Ain(i)) and Bin(i);  
       
      AgB <= s1 or s2 or s3;
      AlB <= s4 or s5 or s6;
    end process calculation;
  end generate;
END ARCHITECTURE structural;

* Error: temp1_structural.vhd(38): Prefix of indexed name must be an array. 
** Error: /temp1_structural.vhd(38): Type error resolving infix expression "and" as type ieee.std_logic_1164.std_logic. 
** Error:temp1_structural.vhd(40): Prefix of indexed name must be an array. 
** Error:temp1_structural.vhd(40): Type error resolving infix expression "and" as type ieee.std_logic_1164.std_logic. 
** Error: temp1_structural.vhd(41): Prefix of indexed name must be an array.
 ** Error: temp1_structural.vhd(41): Type error resolving infix expression "and" as type ieee.std_logic_1164.std_logic. 
** Warning: [2] temp1_structural.vhd(46): (vcom-1090) Possible infinite loop: Process contains no WAIT statement. 
** Error: temp1_structural.vhd(48): VHDL Compiler exiting