I'm suppose to design a gate circuit that tells us weather input is equal to 0 or less than 0. I'm a little stumped on how to design this, I know that from

0-7: Output for equal to 0, this should be true and false for everything else
-8 - (-1) : Output for less than 0, so should be true and false everything else

unless I'm understanding the problem wrong. Also to add this is 2's complement

 

So what do you know about the values of the four bits when the value is positive and when the value is negative?

You said two outputs but so far have only talked about one output that is HI if the input is negative and LO if it is positive or zero. What is the other output?

 

So what do you know about the values of the four bits when the value is positive and when the value is negative?

You said two outputs but so far have only talked about one output that is HI if the input is negative and LO if it is positive or zero. What is the other output?

Oh sorry, that was suppose to be both of the output. So 1 output is : input is equal to 0 and the other one is when input is less than 0.

 

Thanks for the clarification.

Now try to answer the first question. It is key to understanding the whole thing.

 

I know that for 4-bit the left most is the most significant. So when it's 0 it is positive and when its 1 it's negative. I was thinking since it's one from -8 to -1 and putting it on the k-map it would simplify to A (Variables A,B,C,D for 4-bit) so then if we take the complement of that it would be A' but putting that design into work doesn't come up with the right outputs.

 

Why would you take the complement of A? Isn't A what you want since it is HI when the value is less than zero?

Are you saying you wanted to take the complement A and use it as your other signal? If so, keep in mind that you want that signal to be HI when the value is exactly zero, not just when it isn't negative.

 

Yeah, thats what I wanted to do. Take the complement of A and use it as my other output that equals to 0. Oh alright I get it sorta, gonna try come up with a design and post it up

 

Alright I tried and came up with this circuit but 2 of the outputs are wrong



For the circuit eq0 the outputs for +7 - 0 are correct and the rest is false but there is an extra true for -1 which shouldn't be there. Same for the circuit in red (L0) the output for -8 to -2 are correct but -1 shows up false.

A B C D eq0 L0
0 0 0 0 1 0
0 0 0 1 1 0
0 0 1 0 1 0
0 0 1 1 1 0
0 1 0 0 1 0
0 1 0 1 1 0
0 1 1 0 1 0
0 1 1 1 1 0
1 0 0 0 0 1
1 0 0 1 0 1
1 0 1 0 0 1
1 0 1 1 0 1
1 1 0 0 0 1
1 1 0 1 0 1
1 1 1 0 0 1
1 1 1 1 1 0

 

For the L0 output, why are you combining the A signal with anything else at all? You had already determined that L0=A in a prior post. So make L0 equal to A.

Is +5 equal to 0? If not, they how can you say that the eq0 output for pattern 0101 is correct when your table shows it being a 1?

You need to be sure that you have a proper specification for what the circuit is supposed to do before you have any hope of designing a circuit that successfully does it. So what is the eq0 output supposed to tell you? In post #3 above you pretty clearly implied that this output should be HI when the input is exactly equal to 0.

You need to state your specifications clearly and unambiguously. When you say something like "So 1 output is : input is equal to 0 and the other one is when input is less than 0." that is very ambiguous. "the other is" ... what?? Instead, state your specifications something like this:

The input ABCD is treated as a 4-bit two's complement number with A being the msb and D being the lsb. There are two outputs. The first, eq0, should be HI when the input is 0 and LO otherwise. The other, L0, should be HI when the input is less than zero and LO otherwise.

 

For the L0 output, why are you combining the A signal with anything else at all? You had already determined that L0=A in a prior post. So make L0 equal to A.

I was figuring out how to design the circuit from the truth table and got carried away and forgot how L0 should just equal A

You need to be sure that you have a proper specification for what the circuit is supposed to do before you have any hope of designing a circuit that successfully does it. So what is the eq0 output supposed to tell you? In post #3 above you pretty clearly implied that this output should be HI when the input is exactly equal to 0.

You need to state your specifications clearly and unambiguously. When you say something like "So 1 output is : input is equal to 0 and the other one is when input is less than 0." that is very ambiguous. "the other is" ... what?? Instead, state your specifications something like this:

The input ABCD is treated as a 4-bit two's complement number with A being the msb and D being the lsb. There are two outputs. The first, eq0, should be HI when the input is 0 and LO otherwise. The other, L0, should be HI when the input is less than zero and LO otherwise.

Thanks for a clear-up of everything, I'm not really good at explaining stuff but this helps alot. Your revision of the specification is great, here's my finished circuit:


]

 

That's getting closer, but it isn't going to give you want you want. With B, C, and D going into an AND gate, the output of the AND gate is a zero except when all three are HI. Thus the circuit can only distinguish between the three lower bits all being HI and any other condition. You need to distinguish between them all being LO and any other condition.

 

So with the A also going into the AND gate this is going to distinguish all the bits
So the output is HI for eq0 for all A equal to HI and LO otherwise.

 

Again, and AND gate is LO as soon as any one of its inputs is LO. Therefore, if C is LO, it makes absolutely no different whether B and D or LO or HI. But the case you want to single out has all of them LO. But any two of the three can go HI and your circuit output wont change.

Prepare the truth table for what you WANT it to do. How many rows have a HI for the eq0 output?

 

A B C D EQ0 L0 J = ABCD (JA)'
0 0 0 0 1 0 0 1
0 0 0 1 1 0 0 1
0 0 1 0 1 0 0 1
0 0 1 1 1 0 0 1
0 1 0 0 1 0 0 1
0 1 0 1 1 0 0 1
0 1 1 0 1 0 0 1
0 1 1 1 1 0 0 1
1 0 0 0 0 1 0 0
1 0 0 1 0 1 0 0
1 0 1 0 0 1 0 0
1 0 1 1 0 1 0 0
1 1 0 0 0 1 0 0
1 1 0 1 0 1 0 0
1 1 1 0 0 1 0 0
1 1 1 1 0 1 1 0

This is the truth table and 8 rows have HI for eq0. Also to add, I'm using this circuit to implement it with a 4Bit Adder and 2 other circuits to create a ALU with 2 functions: add and subtract.

 

This is the truth table you WANT?

You really WANT eq0 to be 1 for eight different values?

Do you really believe that there are EIGHT values of ABCD in that table that are "equal to 0"?

 

And how are you coming up with your values for (JA)'. If J is only 1 for the last row, then JA must be 0 for ALL of the previious rows, meaning that (JA)' must be 1 for all of the previous rows.

 

And how are you coming up with your values for (JA)'. If J is only 1 for the last row, then JA must be 0 for ALL of the previious rows, meaning that (JA)' must be 1 for all of the previous rows.

That was a typo should be (J+A)'

This is the truth table you WANT?

You really WANT eq0 to be 1 for eight different values?

Do you really believe that there are EIGHT values of ABCD in that table that are "equal to 0"?[/QOUTE]

Well since it's 4bit, so it should be a 16 row truth table. Thats why I set it up like that. But from all the caps your putting in there probably isn't 8 values of ABCD that are "equal to 0" so would a truth table like this work

A B C D
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

 

Try drawing it out in K-map format.

AB\CD |00|01|11|10
00| 0 | 1 | 3 | 2
01| 4 | 5 | 7 | 6
11| 12 | 13 | 15 | 14
10| 8 | 9 | 11 | 10

Fill in the table for 2's compliment

Then look at the logic, it should stare you in the face at that point.

 

That was a typo should be (J+A)'

This is the truth table you WANT?

You really WANT eq0 to be 1 for eight different values?

Do you really believe that there are EIGHT values of ABCD in that table that are "equal to 0"?[/QOUTE]

Well since it's 4bit, so it should be a 16 row truth table. Thats why I set it up like that. But from all the caps your putting in there probably isn't 8 values of ABCD that are "equal to 0" so would a truth table like this work

A B C D
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

There are sixteen rows in the truth table, that's not the problem. Each of those sixteen rows represents a single value in two's complement ranging from -8 to +7. How many of those values are exactly equal to zero? Which ones are they? You want your eq0 signal to be a 1 only for those rows that represent two's complement values that are exactly equal to zero.

Write out your sixteen row truth table and, to the left of it, add a column in which you put the value that each pattern represents in two's complement.

 

@thatoneguy
Thanks, answer was clearly staring at me the moment I starting filling it in

2's | A | B | C | D | (A+B+C+D)'
0000|0 |0 |0 |0| 1
1111|0 |0 |0 |1| 0
1110|0 |0 |1 |0| 0
1101|0 |0 |1 |1| 0
1100|0 |1 |0 |0| 0
1011|0 |1 |0 |1| 0
1010|0 |1 |1 |0| 0
1001|0 |1 |1 |1| 0
1000|1 |0 |0 |0| 0
0111|1 |0 |0 |1| 0
0110|1 |0 |1 |0| 0
0101|1 |0 |1 |1| 0
0100|1 |1 |0 |0| 0
0011|1 |1 |0 |1| 0
0010|1 |1 |1 |0| 0
0001|1 |1 |1 |1| 0

@WBahn

This took me awhile to get... this should be it. eq0 equal to 1 row. Thanks WBahn