I'm having a problem on designing a 4-bit ALU that should take two Twos-complement numbers as input(A and B) with a 2 bit selector.
It should perform like this:
OUTPUT selector
add A and B 00
subtract A and B 01
negate A 10
AND (A anded to B) 11
and aside the 4-bit output, there is also 2 1-bit output. Overflow, which outputs 1 if the result of an addition exceeds the output's capability. Underflow, which outputs 1 if the result of a subtraction is smaller than the output can handle.
I'm still having a problem understanding VHDL.
It should perform like this:
OUTPUT selector
add A and B 00
subtract A and B 01
negate A 10
AND (A anded to B) 11
and aside the 4-bit output, there is also 2 1-bit output. Overflow, which outputs 1 if the result of an addition exceeds the output's capability. Underflow, which outputs 1 if the result of a subtraction is smaller than the output can handle.
I'm still having a problem understanding VHDL.