4-20mA Signal with HART: ADC Resolution Question

Thread Starter

Management

Joined Sep 18, 2007
306
Hi Guys,

HART uses FSK to encode digital information onto 4-20mA analog signals.

So I have a 4-20mA DC signal that has a sine wave at a frequency of 1200Hz for a 1 or 2200Hz for a 0. The sine wave has a 0.5mA peak (100 peak to peak) on top of the 4-20mA DC signal.

See this: http://www.smar.com/hart.asp

What I want to know is will I have enough resolution if I use a 16 bit ADC? Will I have issues with resolving the 1s and 0s? We are doing the filter/separation in the digital domain.

If not what resolution would I need for signal levels mentioned above?

Thoughts on this would be great.
 

beenthere

Joined Apr 20, 2004
15,819
That's the hard way. Use a voltage comparator to square up the signals, and feed a triggered counter for a defined period. The number in the counter will tell you if the freq was 1200 or 2200 Hz.
 

Thread Starter

Management

Joined Sep 18, 2007
306
That's the hard way. Use a voltage comparator to square up the signals, and feed a triggered counter for a defined period. The number in the counter will tell you if the freq was 1200 or 2200 Hz.
From an analog side I don't really care if I have a 1 or a 0. The FPGA will determine that and will be doing a whole bunch of other things.

I do have a a 250 resistor then Diff. Buffer into the ADC.

I just need to know if a 16-bit DAC with a 100 kilo-samples per second update will have the resolution.

Can you help me determine this? Not really a question of how to do it. I really appreciate the suggestion though. And actually would like to talk about it. But just want to answer this question first.

Thanks.
 

beenthere

Joined Apr 20, 2004
15,819
To resolve a waveform, Nyquist suggested that sampling at at least twice the waveform frequency is necessary. So converting at or above 4400 times/sec will be adequate.

If all you need is to distinguish between 1200 & 2200 Hz, 8 bits is way more than enough resolution.
 

Thread Starter

Management

Joined Sep 18, 2007
306
To resolve a waveform, Nyquist suggested that sampling at at least twice the waveform frequency is necessary. So converting at or above 4400 times/sec will be adequate.

If all you need is to distinguish between 1200 & 2200 Hz, 8 bits is way more than enough resolution.
Yes, but the signal level being so low (1 mA p-p) would that be an issue or would that depend on the ADC?

Well considering that the current runs across the 250 Ohm resistor and into a Diff. Buffer then the HART would be at about 250mV peak to peak (1200/2200Hz) at the ADC while the 4-20mA would be (in terms of voltage) 1V to 5V.

Maybe I'm not asking this right but is the 250mV FSK on top of the 1-5V DC too small for an ADC to resolve?

Thanks again for the help.
 
Last edited:
It should work OK; the signal levels are perfectly cromulent w.r.t the HART standard, and 16 bits are more than enough.

The full scale voltage your ADC is referenced to should be 5.125 V or thereabouts*, so 1 bit represents 5.125/65535 = 78 μV (approx). So if the ADC reference is set optimally at 5.125 V then the HART signal will eat up 0.25 V of that, or about 3200 bits. That's more than enough to reconstitute a binary FSK signal.

*5 V represents the 20 mA, plus (250 mV / 2) for the HART signal makes 5.125 V total. Maybe make the ADC reference a little higher by adding on the noise floor voltage too.
 

Thread Starter

Management

Joined Sep 18, 2007
306
It should work OK; the signal levels are perfectly cromulent w.r.t the HART standard, and 16 bits are more than enough.

The full scale voltage your ADC is referenced to should be 5.125 V or thereabouts*, so 1 bit represents 5.125/65535 = 78 μV (approx). So if the ADC reference is set optimally at 5.125 V then the HART signal will eat up 0.25 V of that, or about 3200 bits. That's more than enough to reconstitute a binary FSK signal.

*5 V represents the 20 mA, plus (250 mV / 2) for the HART signal makes 5.125 V total. Maybe make the ADC reference a little higher by adding on the noise floor voltage too.
Great stuff! Thank you so much.
 
You're welcome Management. Don't take my word for it though, check against the micro datasheet as it may not like an ADC Vref that's bigger than Vdd. Scale everything down if need be.

You can get a bit more resolution by subtracting the 4 mA level from the signal the ADC sees, though at 16 bits you shouldn't need to. This assumes you're not using sub-4mA levels for special (non-standard) signalling purposes like fault-flagging etc.
 

Thread Starter

Management

Joined Sep 18, 2007
306
You're welcome Management. Don't take my word for it though, check against the micro datasheet as it may not like an ADC Vref that's bigger than Vdd. Scale everything down if need be.
An ADC has yet to be selected but it is great information to know.

You can get a bit more resolution by subtracting the 4 mA level from the signal the ADC sees, though at 16 bits you shouldn't need to. This assumes you're not using sub-4mA levels for special (non-standard) signalling purposes like fault-flagging etc.
This is true and can be done but in some cases a requirement that HART be disabled and run 0-20mA. I am assuming that this for fault detection.

Again thanks for the help. I will update on this because I really do want to mess this up. This being my over project.
 
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