how to solve this kind of circuit...having 3 stage cascaded....how to solve the voltage gain on the stage A?,,,,thnks....
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He needs to consider the input impedance of the following stage when calculating gain.Simply ignore everything to the right of Q1 to solve for gain of stage A. Solve gain seperately for each stage as though the other two did not exist. Multiply the gains together for overall circuit gain.
You have 3 similar stages. The gain of an unloaded CE stage is about negative Rc/Re in your case, which is about 3.4. The loading between stages must consider the input and output impedeance. The output of your stages is about Rc=3000 and the input impedance is about equal to the bias resistors in parallel if the transistor gain is large. This loading effect gives gain about Rin/(Rin+Rout)= 0.63.how to solve this kind of circuit...having 3 stage cascaded....how to solve the voltage gain on the stage A?,,,,thnks....
This isn't going to work. The DC bias is all wrong. The transistors have no voltage across them to speak of.
There seems to be little point in analyzing the original circuit, as the post is almost 2 years old. Taimour basically hijacked (or maybe hitchhiked onto) an old thread. He has a different problem.You have 3 similar stages. The gain of an unloaded CE stage is about negative Rc/Re in your case, which is about 3.4. The loading between stages must consider the input and output impedeance. The output of your stages is about Rc=3000 and the input impedance is about equal to the bias resistors in parallel if the transistor gain is large. This loading effect gives gain about Rin/(Rin+Rout)= 0.63.
The net effect is 3 gains of 3.4 and two gains of .63 so
Gain=3.4*3.4*3.4*.63*.63=15.6
This is just a quick estimation using ruleofthumb equations. You really need to understand the limitations of the quick formulas that I used here because if you change values some assumptions break down.
However, The Electrician is correct that the biasing is wrong since collector bias current is about 2 times too high and the transistors are in saturation. You need to increase the 16.3K bias resistors to about 36K, or double your Vcc supply voltage to 24V.
Except for the fact that the last stage has no load, while the first two are loaded by the input impedance of the succeeding stage.At midband frequencies you can ignore the loss of voltage across the coupling capacitors. Find the AC gain of the first stage using a transistor model or in any way you want and then raise it to the power of 3 because you have 3 similar stages.
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