how to solve this kind of circuit...having 3 stage cascaded....how to solve the voltage gain on the stage A?,,,,thnks....

 

Simply ignore everything to the right of Q1 to solve for gain of stage A. Solve gain seperately for each stage as though the other two did not exist. Multiply the gains together for overall circuit gain.

 

Simply ignore everything to the right of Q1 to solve for gain of stage A. Solve gain seperately for each stage as though the other two did not exist. Multiply the gains together for overall circuit gain.

He needs to consider the input impedance of the following stage when calculating gain.

 

This is something what we call Darlington Pair? Am I right?

The gain of this is equal to the product of the individual gains of the three transistors. It provides a very high gain of the order of many thousand times.

Can anyone tell me what are those capacitors doing over there?

 

First thing I recommend is you learn how to learn.

second is to find the input impedance to the second stage and work with it like it is Rload in BJT common emitter amplifier design.

 

This isn't going to work. The DC bias is all wrong. The transistors have no voltage across them to speak of.

 

how to solve this kind of circuit...having 3 stage cascaded....how to solve the voltage gain on the stage A?,,,,thnks....

You have 3 similar stages. The gain of an unloaded CE stage is about negative Rc/Re in your case, which is about -3.4. The loading between stages must consider the input and output impedeance. The output of your stages is about Rc=3000 and the input impedance is about equal to the bias resistors in parallel if the transistor gain is large. This loading effect gives gain about Rin/(Rin+Rout)= 0.63.

The net effect is 3 gains of -3.4 and two gains of .63 so
Gain=-3.4*3.4*3.4*.63*.63=-15.6

This is just a quick estimation using rule-of-thumb equations. You really need to understand the limitations of the quick formulas that I used here because if you change values some assumptions break down.

However, The Electrician is correct that the biasing is wrong since collector bias current is about 2 times too high and the transistors are in saturation. You need to increase the 16.3K bias resistors to about 36K, or double your Vcc supply voltage to 24V.

 

This isn't going to work. The DC bias is all wrong. The transistors have no voltage across them to speak of.

You have 3 similar stages. The gain of an unloaded CE stage is about negative Rc/Re in your case, which is about -3.4. The loading between stages must consider the input and output impedeance. The output of your stages is about Rc=3000 and the input impedance is about equal to the bias resistors in parallel if the transistor gain is large. This loading effect gives gain about Rin/(Rin+Rout)= 0.63.

The net effect is 3 gains of -3.4 and two gains of .63 so
Gain=-3.4*3.4*3.4*.63*.63=-15.6

This is just a quick estimation using rule-of-thumb equations. You really need to understand the limitations of the quick formulas that I used here because if you change values some assumptions break down.

However, The Electrician is correct that the biasing is wrong since collector bias current is about 2 times too high and the transistors are in saturation. You need to increase the 16.3K bias resistors to about 36K, or double your Vcc supply voltage to 24V.

There seems to be little point in analyzing the original circuit, as the post is almost 2 years old. Taimour basically hijacked (or maybe hitch-hiked onto) an old thread. He has a different problem.

 

At midband frequencies you can ignore the loss of voltage across the coupling capacitors. Find the AC gain of the first stage using a transistor model or in any way you want and then raise it to the power of 3 because you have 3 similar stages. This is valid for the voltage gain, if you want to find the current gain then things change. You can't find the current gain of the first and raise it to the power of 3 but you need to find the current gain for each stage individually.

 

At midband frequencies you can ignore the loss of voltage across the coupling capacitors. Find the AC gain of the first stage using a transistor model or in any way you want and then raise it to the power of 3 because you have 3 similar stages.

Except for the fact that the last stage has no load, while the first two are loaded by the input impedance of the succeeding stage.

 

I have restored the original posts that were relevant to this thread and have undeleted posts that were deleted as a result of the move.

Apologies for the confusion, and thanks to Ron H for pointing out the errors.

Dave