someone help me to write verilog code for 3 bit up counter
N | A B C |next state
0 | 0 0 0 | 001
1 | 0 0 0 | 001
2 | 0 1 0 | 011
3 | 0 1 1 | 100
4 | 1 0 0 | 101
5 | 1 0 1 | 110
6 | 1 1 0 | 111
7 | 1 1 1 | 000
module up_counter (A,B,C,clk A' B' C')
input clk
output
reg 3:0
0 | 0 0 0 | 001
1 | 0 0 0 | 001
2 | 0 1 0 | 011
3 | 0 1 1 | 100
4 | 1 0 0 | 101
5 | 1 0 1 | 110
6 | 1 1 0 | 111
7 | 1 1 1 | 000
module up_counter (A,B,C,clk A' B' C')
input clk
output
reg 3:0
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