3 Bit Counter J-K FF's

Discussion in 'Homework Help' started by djplayer, Dec 2, 2008.

  1. djplayer

    Thread Starter New Member

    Nov 12, 2008
    decently timely assignment.. at least IMO.

    Design a Bit Synchronous counter that counts 0,2,4,7,0 etc.. when input x=0, and counts 1,2,5,7,1 etc.. when x =1. Use JK FF's to Design the circuit using the listed methods:

    1. SOP
    2. NAND only
    3. POS
    4. NOR only
    5. Minimal # of 1 of 4 mux's plus NOT gates if needed
    6. Minimal # of 3 to 8 line Decoders plus NAND Gates

    essentially I'm just trying to get started right now.. To be honest a decent amount of this is NOT covered in class. Alot is not in the book.

    I found these steps for creation of Synchronous counters:
    -Identify the states and number of states.
    - Calculate # of FF's required. FF = 2^n states.. so I'd be 8
    - I would use the excitation table for JK
    - Construct Truth Table w/ Present, next, excitation inputs for FF
    - Construct K map w/ present state as input and excitation input as ouput
    - Solve K-MAP and obtain the expression for excitation stable input
    - repeat last 2 steps for all inputs

    which sounds all great.. but I haven't even touched the timing diagram. Or the fact that I have to use: SOP, NAND, NOR etc.. etc..

    a little help would be greatly appreciated.
  2. beenthere

    Retired Moderator

    Apr 20, 2004
    You only need 3 flip flops - 0 is 000, 7 is 111. It's a state machine, where the current state plus the X level sets the J & K conditions so the next clock produces the next state.