# 2-bit domino counter without static latches

Discussion in 'Homework Help' started by Sarengo, Apr 5, 2013.

1. ### Sarengo Thread Starter New Member

Apr 5, 2013
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0
Hello,

I'm trying to build a 2-bit domino counter without static latches. A 2-bit counter can be implemented with 2 J-K flip flops but that wouldn't meet the requirement. Is it possible to make a dynamic J-K flip flop?

Assume the JKFF logic is the one with two AND3 gates fed into two NOR2 gates. If I were to make these into dynamic gates, and then into domino logic by feeding them into static inverters, would this work to make a "dynamic JKFF," hence a dynamic latch?

Would the precharge/evaluate phases of the dynamic logic be rendered incorrect through the feedback of the Q and Qnot signals required for the JKFF?

Else: Any other ideas on how to solve the original problem of a 2-bit domino counter without static latches?

~Sarengo

2. ### WBahn Moderator

Mar 31, 2012
24,553
7,691
I know next to nothing about domino logic, but isn't it intended for combinatorial logic and not sequential logic?

I have absolutely no idea what you are talking about here.

3. ### Sarengo Thread Starter New Member

Apr 5, 2013
3
0
The JKFF circuit I am referring to is:

I was attempting to build the below linked 2-bit counter with the JKFF by turning all CMOS gates to domino gates - hence avoiding the restriction of static latches (as I was thinking it would be a dynamic latch):

Upon further thought to my question, a dynamic latch is a paradox anyway, as a latch is supposed to hold values and dynamic logic is transcient (ie. a logic 1 will eventually fall to logic 0 as the capacitances in the circuit discharge). So this probably isn't the way to go for a solution.

Domino logic can be thought of as a dynamic gate followed by a static inverting stage.
http://en.wikipedia.org/wiki/Domino_logic

So a 2-bit domino counter would imply using dynamic gates/stages followed by inverters to obtain my function. However, a counter relies on the previous output value so I would need a feedback loop. But the restriction is that I cannot use static latches to hold values so I'm at a loss as to what options I have...

Using feedback loops with dynamic gates completely throws the logic out the window...anyone have suggestions or thoughts?

~Sarengo

4. ### WBahn Moderator

Mar 31, 2012
24,553
7,691
In the future, if you are going to make reference to a paritcular circuit, please post the circuit you are refering to. We are not mind readers.

The notion of a dynamic latch is not a contradiction. Just as dynamic memory isn't. It just means that the stored value has to be refreshed periodically or it will be lost.

But I think you are going to need to use a latch, be it dynamic or static, to hold your value so that you can control what signal is fed back and ensure that you don't end up with a race condition.

Also, I think you might well find that, in general, dynamic circuits do not lend themselves well to anything other than on-chip designs. I could be wrong, but my guess is that you need pretty well characterized parasitics and propagation delays in order to get them to work reliably.

5. ### Sarengo Thread Starter New Member

Apr 5, 2013
3
0
Yes, I apologize in hindsight. I had been staring at this for too long it seems.

Yes, this is why I am asking for ideas on how to achieve this. I cannot use a static latch by requirement, so it must be a dynamic latch. However, by the time the Q and Qnot are fed back to the inputs as per a flip flop, I've already lost my stored value, which was why I was thinking it was a no-go. Is there another way to dynamically latch this that I'm not seeing...

If the whole circuit precharges in 1 phase, what is saving my state until the next charge...the domino effect from the inverters?

~Sarengo