I am really struggling with designing a three stage BJT. It has the following requirements:
 The input signal shall be a 200 mV peak-to-peak sine wave generated by a standard laboratory signal generator
 The midband gain of the amplifier shall be 50 V/V
 The output signal of the amplifier shall be in phase with the input signal (not inverted)
 The low 3 dB cut-off frequency shall be 20 Hz
 The high 3 dB cut-off frequency shall be 18 kHz
 The supply voltage shall be ±15 V
 The input and output shall be ac coupled to the amplifier
 The BJTs used shall be KSP2222A (NPN) and KSP2907A (PNP)

Any help to start designing this will be much appreciated.

 

Since this is Homework, you need to show your best attempt and we can then help guide you along your journey.

There are some important specs missing from your requirements, such as input/output impedances and the impedance of the load you are expected to drive.

If your amplifier is three stages, what would the gain of each stage need to be if the gain where equally distributed amongst them?

What would it need to be if the gain took place in just the first two stages?

What topologies might you consider for each of the three stages?

 

Welcome to AAC

Remembering this is "Homework Help", as already said, we can only advise on what you show us. However, regarding input/output impedances, ideally they should be specified as this could affect your decisions regarding the topology of each stage., As a starter, you could assume input impedance should, generally, be high and output impedance as low as possible.

 

No input or output impedances were received. Everything I sent is what we received. The load resistance should be 2k2.

The three stages we need to implement are a buffer stage, gain stage and output stage. I am uncertain of which topologies to implement at which stage as I have never done a design like this.

 

I was thinking about starting with a common collector and then a common emitter but I don't know what the last stage should be.

 

I was thinking about starting with a common collector and then a common emitter but I don't know what the last stage should be.

Why?

 

Because a common collector is typically used for voltage buffer and a common emitter for voltage gain

 

Hi GF,
I would suggest you look at designing the 1st input stage and posting your circuit.
E

 

I just don't really know where to start on calculating the component values. Any help on that will be appreciated. And if someone can confirm if my topologies for the different stages are correct or if I should change it, I would also appreciate that.

 

hi GF,
Look at this AAC article for typical example circuits.
E
https://www.allaboutcircuits.com/worksheets/bjt-amplifier-troubleshooting/

 

Okay so this is my circuit but I don't have an idea to calculate values for the components.

 

Because a common collector is typically used for voltage buffer and a common emitter for voltage gain

Why do you think you need a voltage buffer?

If the input is from a standard signal generator, it has 50Ω output impedance. Which means 500Ω input impedance would be fine.

 

hi GF,
Can you calculate the component values that give vc = 15v/2 ..?

E

 

Why do you think you need a voltage buffer?

If the input is from a standard signal generator, it has 50Ω output impedance. Which means 500Ω input impedance would be fine.

Our professor said it was an option to build it with the buffer but we don't have to. So would you suggest I just use three common emitters?

 

Our professor said it was an option to build it with the buffer but we don't have to. So would you suggest I just use three common emitters?

You need to start making your own decisions. Some of them will be poor ones -- but those are the ones you will learn the most from.

Try using your initial circuit topology and see how it goes. If it turns out you chose poorly, you will discover why it was a poor choice and that can then inform your second attempt.

Start with your input stage (everything up to the left side of C2). What voltage do you want to park the DC voltage of the output of this stage at? What constraint does that place on the relationship between R1 and R2?

What is the consequence of choosing Rb1 (and why do you call it Rb_something?) too small? Too large? What value would constitute a balance of not-too-small and not-too-large?

What constraints are there one R1 and R2 so that the your bandwidth limits are violated?

 

hi GF,
Can you calculate the component values that give vc = 15v/2 ..?

E
View attachment 294801

I am not sure if it's correct but I got R1 = 86.144k and R2 = 4.665k

 

hi GF,
How did you calculate the Base current, knowing the BF of a 2N2222 is 200.

Your biassing resistor values drive the transistor into saturation, giving a vc ~ 0.164v. !!

E

 

I used BF = 100 sorry. I got R1 = 1.8M and R2 = 2.2M now but the values seem wrong so I dont know anymore.

 

hi GF,
Those values will give vc ~ 15V/2, BUT as you can image the circuit will be very unstable and unusable.

I have added an 470 ohm Emitter resistor, so recalculate the R1 and R2 values for vc= 15v/2

E

 

hi GF,
Those values will give vc ~ 15V/2, BUT as you can image the circuit will be very unstable and unusable.

I have added an 470 ohm Emitter resistor, so recalculate the R1 and R2 values for vc= 15v/2

EView attachment 294807

I calculated R1= 100k and R2 = 10k