I was trying to design a 2x1 MUX using a CMOS logic. I have used a 180nm library for the mosfets and made the circuits using Transmission gates. For simulation purposes, I have considered Width of PMOS as 3 times the width of NMOS. When S = 0 then the output should be D0 and when S = 1 the output should be D1 but I am having some change in voltage levels in my output. When I run the simulation, I am getting this error but most of my previous circuits worked even with this error. So I don't think this has anything to do with the output. Please let me know what the problem is.
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My guess is that you IGNORED the LTspice HELP file which details the MOSFET model levels that it handles. Given the number of error messages that it threw I think you might be out of luck.

M. MOSFET ​

There are seven monolithic MOSFET device models. The model parameter LEVEL specifies the model to be used. The default level is one.​

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level model​

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1 Shichman-Hodges​

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2 MOS2(see A. Vladimirescu and S. Liu, The Simulation of MOS Integrated Circuits Using SPICE2, ERL Memo No. M80/7, Electronics Research Laboratory University of California, Berkeley, October 1980)​

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3 MOS3, a semi-empirical model(see reference for level 2)​

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4 BSIM (see B. J. Sheu, D. L. Scharfetter, and P. K. Ko, SPICE2 Implementation of BSIM. ERL Memo No. ERL M85/42, Electronics Research Laboratory University of California, Berkeley, May 1985)​

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5 BSIM2 (see Min-Chie Jeng, Design and Modeling of Deep-Submicrometer MOSFETs ERL Memo Nos. ERL M90/90, Electronics Research Laboratory University of California, Berkeley, October 1990)​

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6 MOS6 (see T. Sakurai and A. R. Newton, A Simple MOSFET Model for Circuit Analysis and its application to CMOS gate delay analysis and series-connected MOSFET Structure, ERL Memo No. ERL M90/19, Electronics Research Laboratory, University of California, Berkeley, March 1990)​

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8 BSIM3v3.3.0 from University of California, Berkeley as of July 29, 2005​

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9 BSIMSOI3.2 (Silicon on insulator) from the BSIM Research Group of the University of California, Berkeley, February 2004.​

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12 EKV 2.6 based on code from Ecole Polytechnique Federale de Lausanne. See http://legwww.epfl.ch/ekv and "The EPFL-EKV MOSFET Model Equations for Simulation, Version 2.6", M. Bucher, C. Lallement, F. Theodoloz, C. Enz, F. Krummenacher, EPFL-DE-LEG, June 1997.​

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14 BSIM4.6.1 from the University of California, Berkeley BSIM Research Group, May 18, 2007.​

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73 HiSIMHV version 1.2 from the Hiroshima University and STARC.​

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That may not be the whole story since I have level 49 models that seem to work fine. Here is one of them. Try this to see if it works for you, and we can go from there.

 

Look at your Sbar signal to confirm that it looks like what you want it to look like.

In general, I'd recommend running generated signals through inverters/buffers made using the same technology as your devices so that you get more realistic impedances, drive strengths, and edge speeds.

You should also tie your transistor bulks more realistically. Unless you are using a twin-well process, the bulks on one type (the NFET in a P-Well process) will be tied to the substrate. Also, if your two PFETs are in the same well, then you will be shorting your two input signals via the well connection. Tie your well connections to the power supply.