Hi all,
Is the maximum load capacitance in any way related to the configurable drive strength on output pin?
This is what I understand -
1. As long as the total output capacitance of input pins are below the max capacitance of the output pin, the AC specification of the chip will be valid.
2. When the total output capacitance exceeded the max capacitance of the output pin, we need to check on the delay due to this additional capacitance. For slower speed communication, this should be fine assuming we are operating within the timing specification.
3. Setting a higher drive strength would decrease the rise/fall time.

Question -
Does setting higher drive strength helps to reduce the delay caused by high total load capacitance?
How are these two related or are they related at all?

Thanks.
kakiitek

 

How are these two related or are they related at all?

Of course they are.

The rise/fall time of the capacitive load is related to the output source/sink drive current by the standard capacitor equation dv/dt = C/I where I is the current.

 

Slow rise and fall times with MSOFET circuitry not not only cause delay in switching but also increased power dissipation because the longer the transition the longer the MOSFETs are conducting current with a significant voltage across them.

 

A good "Circuit-Simulator" Software-Program will let You play-around with different
scenarios/values of Drive-Amplifier-Impedance -vs- Capacitive-Loads.

Generally, you almost can't have a "too-low" of a Drive-Impedance,
unless it starts to cause excessive "Ringing" or "Oscillations"
that may cause un-wanted Circuit behavior.

Many times Circuits are designed with what is determined to be
an Output-Impedance that is just barely "good enough" to
meet most of the design-goals of the particular Circuit,
because less Drive-Current usually means less expensive, and possibly smaller, components.
It may also be a Power-consumption consideration when designing Battery-Powered-Circuits.
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