Hello
I have a practical this Monday and urgently need too design a 4-bit up/down counter with D flip flops with very limited gates. I was told to essentially merge an up counter and down counter that I had created (attached below). My own reasoning and examples online indicate the best way to merge these would be with a multiplexer made from the NAND gates but I only have 4 and I believe I need a minimum of 7.
below are my simulations, my working UP counter, working DOWN counter and all available components for the UP/DOWN counter. (ignore the unused connections that are grounded, the simulator is fussy about it).
Any help would be appreciated, thank you
I have a practical this Monday and urgently need too design a 4-bit up/down counter with D flip flops with very limited gates. I was told to essentially merge an up counter and down counter that I had created (attached below). My own reasoning and examples online indicate the best way to merge these would be with a multiplexer made from the NAND gates but I only have 4 and I believe I need a minimum of 7.
below are my simulations, my working UP counter, working DOWN counter and all available components for the UP/DOWN counter. (ignore the unused connections that are grounded, the simulator is fussy about it).
Any help would be appreciated, thank you
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