I am trying to understand clock stretching. I guess clock signals is a square wave oscillating digital signals that microcontroller sends to slave device
What's clock stretching in contexts of serial communication protocol.

 

I am trying to understand clock stretching. I guess clock signals is a square wave oscillating digital signals that microcontroller sends to slave device
What's clock stretching in contexts of serial communication protocol.

In I2C protocol, pull-up resistors are required on the signals. That allows the slave device to stop the clock signal if it needs more time to complete an action before sending a signal. The clock input can be connected to another pin that is switched from an input to an output low (or the clock pin itself on the slave can be converted to an output low). This logic low stops the clock on the serial communication because the master device must check its clock signal that it is actually "high" before going low for the next instruction.

When the slave device pauses the masters clock signal as described, this is called clock stretching.

 

In I²C communications if the slave needs more time to respond to the master it can pull the SCL line low to “stretch the clock” letting the master know it is processing the data then it releases SCL and responds as usual.

It lets the slave avoid failing to reposed to a request because it’s not ready. It is like the CTS (Clear To Send) pin on an RS-232 interface which notifies the DCE (Data Communications Equipment) end of the exchange that the DTE (Data Terminal Equipment) end is ready to receive data in function, though CTS is part of an explicit handshaking process.

 

In a synchronous network such as CAN, the transmitter and receiver derive their clock signals from crystals with different frequencies. Over the length of a CAN frame the transmit bits and the receive bits will become mis aligned. The CAN controller has a way of resynchronizing (stretching or contracting) the receive clock to the transmit data stream by adding or subtracting small increments, typically 1/16 of a bit period, to the receive clock. This mechanism is completely under the hood and implemented in hardware. It is very difficult to see with typical test equipment.

 

In the clock signals I see there are two transactions low-to-high called the rising edge and high-to-low called the falling edge.

My guess here is when we say, capture data on rising edge of clock it means store data when clock goes from high to low. I don't understand what it means when we say, data is propagated on high-to-low clock transition.

 

In the clock signals I see there are two transactions low-to-high called the rising edge and high-to-low called the falling edge.

My guess here is when we say, capture data on rising edge of clock it means store data when clock goes from high to low. I don't understand what it means when we say, data is propagated on high-to-low clock transition.

You can define the bit as happening on the rising edge of the waveform or the falling edge. If you say "data is propagate on the high-to-low transition" that is saying the bit is indicated by the falling edge. The waveform rises from the low logic level to the high logic level and falls from the high to the low, as with all things moving between heights.

I think the falling edge will tend to be more reliable because of the overshoot that can happen on the rising edge, but I really don't know if that is correct.

 

You can define the bit as happening on the rising edge of the waveform or the falling edge. If you say "data is propagate on the high-to-low transition" that is saying the bit is indicated by the falling edge. The waveform rises from the low logic level to the high logic level and falls from the high to the low, as with all things moving between heights.

I think the falling edge will tend to be more reliable because of the overshoot that can happen on the rising edge, but I really don't know if that is correct.

Overshoot arises from the lack of damping, and it happens on both edges

 

Overshoot arises from the lack of damping, and it happens on both edges

I was thinking that the overshoot on the rising edge, followed by ringing, would be more ambiguous than the droop on the falling edge since there are no addition upward movements in the voltage. But as I said, it was speculative. I was thinking about the classic pulse waveform profile.

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You can define the bit as happening on the rising edge of the waveform or the falling edge. If you say "data is propagate on the high-to-low transition" that is saying the bit is indicated by the falling edge. The waveform rises from the low logic level to the high logic level and falls from the high to the low, as with all things moving between heights.

I still do not get it. I am referring to the data as bit.

-> The data is captured on the low-to-high clock transition.

Is the value of the bit stored on the rising edge?

-> The data is propagated on high-to-low clock transition.

I still don't understand the meaning of this statement

 

I still do not get it. I am referring to the data as bit.

-> The data is captured on the low-to-high clock transition.

Is the value of the bit stored on the rising edge?

-> The data is propagated on high-to-low clock transition.

I still don't understand the meaning of this statement

IN that case a bit is received on the riding edge and sent on the falling edge. Where is the description from?

 

I was thinking that the overshoot on the rising edge, followed by ringing, would be more ambiguous than the droop on the falling edge since there are no addition upward movements in the voltage. But as I said, it was speculative. I was thinking about the classic pulse waveform profile.

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In an ideal 2nd order RLC system the rising and falling edges should be the same. If they are different, it is due to non-ideal parasitic elements that affect the rising and falling edges differently.

 

IN that case a bit is received on the riding edge and sent on the falling edge. Where is the description from?

I understood, thank you. When I read about spi protocol these term's are used in description.

 

The software statement for serial communication to cause stretching is "Wait" so the next question might be "what does s-t-r-e-t-c-h-ing look like?"
A logic analyzer allows visual representation of the data line signals, The video shows serial data using computer software.
Some oscilloscopes had this feature traditionally. Programming and debugging has more serial port functions now.
Because of the growing number of peripheral types that you can sample the differences and variety needs a description to include all the stuff.
A cheap LA (logic analyzer} cost less than $10