Please help me with operation of the FMC module in STM32F407VE. It is necessary to connect external RAM memory; since FMC module in this microcontroller uses the address bus and data bus in muxed mode, its need to demultiplex this signals. For this purpose the nADV (nL) signal is used. This signal must route to external latches.
It is assumed to use RAM type IS61LV25616AL or something similar. Datasheet is here:
https://datasheet.lcsc.com/lcsc/180...ilicon-Solution-IS61LV25616AL-10TL_C16001.pdf
My questions:
1) Timing diagrams are shown only for accessing NOR FLASH in the Reference Manual (RM0090). It can be expected that in general timing diagrams should be the same for PSRAM (RM0090, see page 1547). However, it is not very clear on which edge the address bus should be latched. I suppose that address bus should be latched on rising edge; precisely during time between the falling and rising edges of the nADV (nL) signal the transients on traces must end and then the FMC module samples the data (for read mode). If this true, the two 74HC574 chip can be used to latch address.
By the way this IC is rather slow. Delay between input and output can be over 200 ns with a 2 V supply, and 45 ns with a 4.5 V supply. Although my circuit will operate on a 3.3 V supply, the delay will still remain big enough. Maybe I should look for something faster?
2) Since the data bus is 16-bit width FMC will use split access to call 32-bit data (RM0090, see page 1533). I wonder what consequences I should expect in this case besides the increase in the data access time compared to the data access time in the internal memory. Also is it true that good practice not to make calls to external memory from interrupt routines, and as a last resort - to use the __DSB () instruction?
3) The data line would be in a high-Z state for a short time in the multiplexed mode, as well as during byte-by-byte access. Should I pull these lines to the ground or power with 1…10k resistors?
It is assumed to use RAM type IS61LV25616AL or something similar. Datasheet is here:
https://datasheet.lcsc.com/lcsc/180...ilicon-Solution-IS61LV25616AL-10TL_C16001.pdf
My questions:
1) Timing diagrams are shown only for accessing NOR FLASH in the Reference Manual (RM0090). It can be expected that in general timing diagrams should be the same for PSRAM (RM0090, see page 1547). However, it is not very clear on which edge the address bus should be latched. I suppose that address bus should be latched on rising edge; precisely during time between the falling and rising edges of the nADV (nL) signal the transients on traces must end and then the FMC module samples the data (for read mode). If this true, the two 74HC574 chip can be used to latch address.
By the way this IC is rather slow. Delay between input and output can be over 200 ns with a 2 V supply, and 45 ns with a 4.5 V supply. Although my circuit will operate on a 3.3 V supply, the delay will still remain big enough. Maybe I should look for something faster?
2) Since the data bus is 16-bit width FMC will use split access to call 32-bit data (RM0090, see page 1533). I wonder what consequences I should expect in this case besides the increase in the data access time compared to the data access time in the internal memory. Also is it true that good practice not to make calls to external memory from interrupt routines, and as a last resort - to use the __DSB () instruction?
3) The data line would be in a high-Z state for a short time in the multiplexed mode, as well as during byte-by-byte access. Should I pull these lines to the ground or power with 1…10k resistors?
